TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 601

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SPI
20.4.1. SPI Master Control Register (SPMCR)
Rev. 3.1 November 1, 2005
Bit(s)
31 : 8
7 : 6
5
4
3
2
1
0
Default:
Default:
Name:
Name:
R/W:
R/W:
Bit:
Bit:
Mnemonic
⎯
OPMODE
⎯
SPICSENB
SPICSOUT
⎯
SPSTP
BCLR
31
15
30
14
29
13
Field Name
Reserved
Operation Mode
Reserved
Chip Select
Enable
Chip Select
Reserved
SPI Stop
SPI Buffer Clear
RESERVED
28
12
Figure 20-4 SPI Master Control Register (SPMCR)
Table 20-4 SPI Master Control Register (SPMCR)
27
11
Description
⎯
Operation Mode (Default: 01)
Sets the operation mode.
00: Don’t care.
01: Configuration Mode
10: Active Mode
11: Sleep Mode
⎯
Chip Select Enable (Default 1’b1)
1’b1: Chip Select (SPICSOUT) disabled
1’b0: Chip Select (SPICSOUT) enabled
Chip Select (Default: 1’b1)
1’b1: Active high Chip Select
1’b0: Active low Chip Select
Do not write “1” to this bit.
SPI Stop (Default: 0)
When “1” is written to this bit, the SPI Module does not transfer any more data after
the current frame is complete. You can only set this bit when in the Active Mode.
Entering the Configuration Mode clears this bit.
0: Normal operation
1: Halt after the current transfer ends.
SPI Buffer Clear (Default: 0)
Use this bit to clear the Transmitter FIFO and Receiver FIFO. Writing “1” to this bit
initializes the FIFO. Write “1” to this bit after the SPI Module enters the Idle state
(SIDLE=1). BCLR can be asserted only if SPSTP has already been asserted.
Always outputs “0” when read.
Write:
0: Don’t care
1:Clear the FIFO
26
10
25
9
20-9
RESERVED
24
8
R/W
23
OPMODE
7
0
R/W
22
6
1
21
5
SPICSENB SPICSOUT
R/W
1’b1
20
Toshiba RISC Processor
4
R/W
1’b1
19
3
0xF800
R/W
18
⎯
2
0
SPSTP
R/W
17
1
0
TX4939
BCLR
R/WC
16
0
0
20
20