TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 615

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

I2C
22.2.4. I2C Prescale Register (I2C_PRE)
22.2.4.1. Prescale Register
Register I2C_PRE[15:0] are used to prescale the SCL clock line. Due to the structure of the I
a 5*SCL clock internally. The prescale register must be programmed to this 5*SCL frequency (minus 1). Change the
value of the prescale register only when the “I2C mode” is disable.
Example: wb_clk_i = 32MHz, desired SCL = 100KHz
Reset value: 0xFFFF
Rev. 3.1 November 1, 2005
prescale
Bit
31:16
15:0
Reset Value
Reset Value
R/W/RO
R/W/RO
=
Bit
Bit
5
∗
32
100
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
RO
MHz
31
15
0
1
KHz
Field Name
Reserved
Prescale
RO
30
14
0
1
RO
29
13
−
0
1
1
RO
28
12
=
0
1
63
Description
Reserved
Prescale
prescale = [ IMBusCLK / (5 * SCL) ] - 1
RO
27
11
[15:8] = Clock Prescale register hi-byte
0
1
[7:0] = Clock Prescale register lo-byte
(
dec
RO
26
10
0
1
)
22-5
=
RO
25
0
9
1
3
F
RO
24
0
8
1
(
hex
RO
23
0
7
1
)
RO
22
0
6
1
RO
21
5
0
1
RO
20
0
4
1
Toshiba RISC Processor
RO
19
3
0
1
2
C interface, the core uses
RO
18
0
2
1
0xF90C
RO
17
1
0
1
RO
16
0
0
1
TX4939
22
22