TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 617

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

I2C
22.3. System Configuration
The I2C system uses a serial data line (SDA) and a serial clock line (SCL) for data transfers. All devices connected to
these two signals must have open drain or open collector outputs. The logic AND function is exercised on both lines with
external pull-up resistors.
The I2C core is a single master device; therefore, it starts generating a clock as soon as it is released from reset, this
being the slowest clock possible (Clock Prescale = 0xFFFF). The user should program this register to the desired value
before starting any transfers.
Data is transmitted synchronously to SCL on the SDA line on a byte-by-byte basis. Each data byte is 8bits long. There is
one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred
byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low
period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is
interpreted as a command (see START and STOP signals).
22.3.1. I2C Protocol
Normally, a standard communication consists of four parts:
22.3.2. START signal
When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master
can initiate a transfer by sending a START signal. A START signal, usually referred to as the S-bit, is defined as a high-
to-low transition of SDA while SCL is high. The START signal denotes the beginning of a new data transfer.
A Repeated START is a START signal without first generating a STOP signal. The master uses this method to
communicate with another slave or the same slave in a different transfer direction (e.g. from writing to a device to reading
from a device) without releasing the bus.
The core generates a START signal when the STA-bit in the Command Register is set and the RD or WR bits are set.
Depending on the current status of the SCL line, a START or Repeated START is generated.
22.3.3. Slave Address Transfer
The first byte of data transferred by the master immediately after the START signal is the slave address. This is a seven-
bits calling address followed by a RW bit. The RW bit signals the slave data transfer direction. No two slaves in the
system can have the same address. Only the slave with an address that matches the one transmitted by the master will
respond by returning an acknowledge bit by pulling the SDA low at the 9th SCL clock cycle.
Note: The core supports 10bit slave addresses by generating two address transfers. See the Philips I2C specifications
for more details.
The core treats a Slave Address Transfer as any other write action. Store the slave device’s address in the Transmit
Register and set the WR bit. The core will then transfer the slave address on the bus.
Rev. 3.1 November 1, 2005
SCL
SDA
(1) START signal generation
(2) Slave address transfer
(3) Data transfer
(4) STOP signal generation
S
A7 A6 A5 A4 A3 A2 A1
Figure 22-2 I2C Protocol
22-7
RW ack D7 D6 D5 D4 D3 D2 D1 D0
Toshiba RISC Processor
nack
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