TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 62

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Features
1.3. System Block Diagram
Figure 1-1 System Block Diagram shows TX4939 implemented features.
Due to pin limitation, some of features are not used simultaneously.
Rev. 3.1 November 1, 2005
Default Signal Name Default Function
ATA100-0
ATA100-1
Video Port
SPI Port
ACLINK
I2C
General-Purpose
Audio Clock
Clock Gen
EJTAG
Modulator
400MHz
800MHz
EJTAG IF
DSU
MAC Circuit
TEST
SSCG
PLL#1
PLL#2
PLL#3
JTAG
Data Bus
&
Register
Integer Operation Unit
TX49/H4 CPU Core
Ins. Cache
4-W.S.A
Descriptor
32KB
Engine
3DES
SHA1
Drive
DMA
DES
MD5
AES
Pipeline
Control
PCI 32bit 33/66MHz
Buffer
Write
GPIO Ch-0 (30p)
GPIO Ch-1 (30p)
GPIO Ch-2 (17p)
GPIO (4p)
GPIO (6p)
GPIO (2p)
De-Skew
PLL#4
Table 1-1 Major Functional IPs shared by pin multiplexing.
CP0 Register
Handling Unit
PCIC
PGB
MMU/TLB
Exception
Ins. Cache
4-W.S.A
CP0
CP1
FPU
32KB
PCICLK
Figure 1-1 System Block Diagram
ATA100/GPIO
Primary Function
ATA100/ATAPI CH-0
ATA100/ATAPI CH-1
1-Serial TS I/O,
1-Parallel TS/656 I/O
SPI Interface
ACLINK
I2C
G-BUS 64 bit 200 MHz
ATA100
G-BUS
Bridge
CH-0
14-address signals
DDR-SDRAM
2-chip selects
DDR IO
Controller
2-banks
32-bits
1-Paralell IO
1-2
Video Port
3-Serial In
VIDEO
G-BUS
PORT
Bridge
DDR CLK
SYSCLK
External Bus Control
(NAND Flash)
Secondary Function
N/A
Max. 2-ch 10/100 Ethernet MAC
with RMII interface
1-Serial TS I/O,
2-Serial TS Input
SIO2, SIO3
I2S 2ch / I2S 5.1ch
N/A
ATA100
G-BUS
Bridge
CH-1
External Bus
SRAM
ATA100 / GPIO / RMII
2KB
eMAC1
10/100
(Interrupt)
Internal PCI
Internal PCI
IRC
DMAC
DMAC
Chain
mode
PCIC1
8-ch
PGB1
Toshiba RISC Processor
eMAC0
10/100
INT
(5.1ch & 2ch)
RTC
Battery
Battery Back
ACLINK
Control
SIO-0
SIO-1
SIO-2
SIO-3
Timer
WDT
SPI
I2C
I2S
Back-
TX4939
Rev 2.27
-
UP
UP
1
1

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