TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 624

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

I2C
22.9.2. Example 2 (Byte Mode)
Read a byte of data from an I2C memory device.
Slave address = 0x4E
Memory location to read from = 0x20
I2C sequence:
Commands:
Rev. 3.1 November 1, 2005
SCL
SDA
SCL
SDA
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) write no acknowledge (NACK) to slave, indicating end of transfer
(11) generate stop signal
(1)
(2)
(3)
(4)
generate start signal
write slave address + write bit
receive acknowledge from slave
write memory location
receive acknowledge from slave
generate repeated start signal
write slave address + read bit
receive acknowledge from slave
read byte from slave
write 0x9C (address + write bit) to Transmit Register, set STA bit, set WR bit.
read I2C_ASTS (ACK) bit from Control/Status Register, should be ‘0’.
write 0x20 to Transmit register, set WR bit.
read I2C_ASTS (ACK) bit from Control/Status Register, should be ‘0’.
write 0x9D (address + read bit) to Transmit Register, set STA bit, set WR bit.
set RD bit, set ACK to ‘1’ (NACK), set STO bit
R
S
-- wait for interrupt or I2C_DSTS (done) flag to negate --
-- wait for interrupt or I2C_DSTS (done) flag to negate --
-- wait for interrupt or I2C_DSTS (done) flag to negate --
-- wait for interrupt or I2C_DSTS (done) flag to negate --
Third Command
First Command
Figure 22-8 Byte Mode
22-14
Wr ack
Rd
ack
D7 D6 D5 D4 D3 D2 D1 D0
Second Command
Forth Command
Toshiba RISC Processor
nack
ack
P
TX4939
22
22