TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 630

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

I2S
23.2.2. Mode of operation
There are two modes of operation
2 channel i/o mode
3 channel output mode
For 2 channels i/o mode: there are two pairs (SCK, WS, SD) of i2s signal. These two channels can be program to be input
or output. At reset, default will be input mode.
For 3 channel output mode: There are common SCK,WS and separate three data line (SD0, SD1, SD2). SCK0 and WS0
are the common SCK and WS. WS1 becomes SD2. And SCK1 is not use. The following is the pin mux table
Rev. 3.1 November 1, 2005
Signal name/Mode
I2S_SCK0
I2S_SCK1
I2S_WS0
I2S_WS1
I2S_SD0
I2S_SD1
2 Channel i/o Mode
I2S_SCK0
I2S_SCK1
I2S_WS0
I2S_WS1
I2S_SD0
I2S_SD1
23-6
3 Channel Output Mode
I2S_SCK
I2S_SD0
I2S_SD2
I2S_SD1
I2S_WS
N/A
Toshiba RISC Processor
TX4939
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