TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 637

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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I2S
Rev. 3.1 November 1, 2005
Bit
D16
D15:12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2:1
D0
Field Name
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Description
Channel 1 i/o Mode Option
When 3 Channel Mode is enable, this bit is not used.
Reserved.
WS Check Enable (Channel 0 i/o and 3 Channel Output mode)
MCLK Check Enable (Channel 0 i/o and 3 Channel Output mode)
Clock Data Option (Channel 0 i/o and 3 Channel Output mode)
Notes:
Falling edge selected: WS is toggle at the falling edge of SCK
Rising edge selected:
Output mode:
Input mode:
Data Swap Option (Channel 0 i/o and 3 Channel Output mode)
MCLK Mode Option (Channel 0 i/o and 3 Channel Output mode)
Receiver-Master Mode Option (Channel 0 i/o and 3 Channel Output
mode)
Clock Delay Option (Channel 0 i/o and 3 Channel Output mode)
For Left-Justify mode only
Invert WS Option (Channel 0 i/o and 3 Channel Output mode)
Left/Right Justify Select Option (Channel 0 i/o and 3 Channel Output
mode)
Data Select Option (Channel 0 i/o and 3 Channel Output mode)
Channel 0 i/o Mode Option
When 3 Channel Output Mode is enable, this bit is not used.
Falling edge selected: clock SD
Rising edge selected: clock SD at rising edge
Falling edge selected: sample SD at rising edge
Rising edge selected: sample SD
23-13
0: Output channel mode
1: Input channel mode (default)
0: Disable (default)
1: Enable
0: Disable (default)
1: Enable
0: Falling edge (default)
1: Rising edge
0: Left-Justify (default)
1: Right-Justify
00: 16 bits data (default)
01: 18 bits data
10: 20 bits data
0: Output channel Mode
1: Input channel Mode(default)
11: 24 bits data
0: Normal (default)
1: Swap (MSB <--> LSB)
0: Slave mode. Receive MCLK0
1: Master mode. Drive MCLK0 (Default)
0: Slave mode. Receive SCK, WS
1: Master mode. Drive SCK, WS (Default)
0: Latch data on the first clock (default)
1: Latch data on the second clock
0: As normal (default)
1: Invert WS
WS is toggle at the rising edge of SCK
at falling edge
at falling edge
Toshiba RISC Processor
TX4939
23
23

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