TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 649

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Toshiba RISC Processor
ACLINK
TX4939
24.3.3. AC-link Start Up
Figure 24-6 shows the conceptual sequence of AC-link start-up.
The ACLC Control Enable Register’s Enable AC-link bit is used to deassert/assert the ACRESET* signal to the link side
(including AC-link).
This bit defaults to ‘0’, so the CPU asserts the ACRESET* signal when it boots up.
The AC’97 specification requires that the reset assertion period is 1µs or longer.
The software is responsible for
controlling the length of this period.
24
24
The AC’97 specification also requires that the primary CODEC stops the AC-link clock (BITCLK) signal during the period
from ACRESET* signal assertion to 162.8ns after ACRESET* signal deassertion.
ACLC assumes the primary CODEC
meet this requirement.
Deasserting the link-side reset makes the primary CODEC start driving the BITCLK signal.
When the BITCLK signal is
provided, ACLC starts the SYNC signal output, which indicates the start of the AC-link frame, and starts the frame-length
counting.
When a CODEC becomes ready to receive access to its own register, the CODEC sets the “CODEC Ready” bit of the
Tag slot.
When ACLC detects that this bit has been set, the ACLC Interrupt Status Register (ACINTSTS)’s CODEC[1:0]
Ready (CODEC[1:0]RDY) bit is set.
The system software is able to recognize the readiness of the CODEC(s) by
detecting this event by way of either polling or interrupt.
In case of 5.1 channel audio connection example (Figure 24-3), because the secondary CODEC is connected to the
SDIN1 signal of ACLC, the software must watch ACINTSTS.CODEC1RDY bit to determine the CODEC’s readiness for
the register access.
ACRESET*
BITCLK
SYNC
SDIN
ENLINK
CODECRDY
Bo
Software sets ENLINK bit
ACLC internal clock becomes active
CODEC becomes ready to accept register access
Note: The number of BITCLK cycles relative to other signals is not to scale.
Figure 24-6 Cold Reset and CODEC Ready Recognition
Rev. 3.1 November 1, 2005
24-7

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