TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 652

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ACLINK
24.3.6. DMA Channel Mapping
ACLC uses four DMA request channels.
on the AC-link frame, according to ACLC DMA Channel Selection Register (ACDMASEL) setting as shown in Table 24-1.
The pin configuration register allocates these DMA channels of ACLC to the DMAC (DMA controller) channels according
to Pin Configuration Register (PCFG)’s DMA Request Selection (DMASEL[7:0]) bits as described in section 5.1.3.
24.3.6.1. Sample-data Format
ACLC transmits/receives 16 bits per sample for each data slot shown in Table 24-1. The data resides on the first 16 bits
of the 20 bits assigned to each slot on AC-link. Each sample-data register allows access by word (32-bit) unit only.
Therefore the DMA count must be a multiple of word.
depth (refer to ***) or more for a reason described later.
For audio PCM front and surround streams, every data-word is loaded with a couple of left and right samples.
audio MIC stream, valid data is loaded in the same field as the left sample while the other field is filled with ‘0’.
audio center, LFE, and modem line 1 streams, two consecutive samples are packed into every word.
The data format at the sample-data register is arranged so that the data format on the DMA buffer follows the rules
below.
Refer to the later section for the register format.
Rev. 3.1 November 1, 2005
Each sample data is put in the byte order in which the CPU operates (big- or little-endian).
Samples are put in the time-sequential order at increasing addresses on memory.
For a DMA channel which couples left and right samples, each left sample precedes the corresponding right
sample.
PCM L&R in (3&4) or Mic in (6)
AC-link Slot Number
Surround L&R out (7&8)
Modem Line1 out (5)
PCM L&R out (3&4)
Modem Line 1 in (5)
Center out (6)
LFE out (9)
Table 24-1 DMA Channel Mapping Modes
These DMA channels are allocated to four out of seven data-streams, or slots,
ACLC ch1
ACLC ch3
ACLC ch0
ACLC ch2
0
24-10
Note that the transmit-data DMA count also must be the FIFO
ACLC ch3
ACLC ch0
ACLC ch1
ACLC ch2
1
ACDMASEL
ACLC ch0
ACLC ch1
ACLC ch2
ACLC ch3
2
Toshiba RISC Processor
ACLC ch0
ACLC ch1
ACLC ch3
ACLC ch2
3
TX4939
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