TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 659

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ACLINK
24.4.1. ACLC Control Enable Register
This register is used to check the setting of various ACLC features and to enable them.
Rev. 3.1 November 1, 2005
Bit
31:24 ⎯
23
22
21
20
19
Default:
Default:
Name:
Name:
R/W:
R/W:
Bit:
Bit:
Mnemonic
MODIEHLT
MODOEHLT
⎯
AUDIEHLT
LFEEHLT
R/W1S R/W1S
MODI
DMA
31
15
0
MODO
DMA
30
14
0
Field Name
Reserved
Enable Modem
Receive-data DMA
Error Halt
Enable Modem
Transmit-data
DMA Error Halt
Reserved
Enable Audio
Receive-data DMA
Error Halt
Enable Audio LFE
Transmit-data
DMA Error Halt
Reserv
29
13
ed
AUDID
R/W1S R/W1S R/W1S R/W1S R/W1S
MA
28
12
Reserved
0
LFED
MA
27
11
Description
MODIEHLT: Enable Modem Receive-data DMA Error Halt.
MODOEHLT: Enable Modem Transmit-data DMA Error Halt.
AUDIEHLT: Enable Audio Receive-data DMA Error Halt.
LFEEHLT: Enable Audio LFE Transmit-data DMA Error Halt.
0
R
W1S
R
W1S
R
W1S
R
W1S
Figure 24-9 ACCTLEN Register
Table 24-11 ACCTLEN Register
CENT
DMA
26
10
0
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
SURR
DMA
25
Indicates that MODIDMA error halt is disabled.
Indicates that MODIDMA error halt is enabled.
No effect
Enables MODIDMA error halt.
overrun occurs, subsequent DMA will not be issued.
Indicates that MODODMA error halt is disabled.
Indicates that MODODMA error halt is enabled.
No effect
Enables MODODMA error halt.
underrun occurs, subsequent DMA will not be issued.
Indicates that AUDIDMA error halt is disabled.
Indicates that AUDIDMA error halt is enabled.
No effect
Enables AUDIDMA error halt.
overrun occurs, subsequent DMA request will not be
issued.
Indicates that LFEDMA error halt is disabled.
Indicates that LFEDMA error halt is enabled.
No effect
Enables LFEDMA error halt.
underrun occurs, subsequent DMA request will not be
issued.
9
0
24-17
AUDO
DMA
24
8
0
MODIE
R/W1S R/W1S
HLT
23
Reserved
0
7
MODO
EHLT
W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S
22
0
6
0
Reserv
RDYC
LR
When LFEDMA
21
ed
5
0
When AUDIDMA
When MODIDMA
When MODODMA
R/W1S R/W1S R/W1S R/W1S R/W1S
MICSE
AUDIE
HLT
20
Toshiba RISC Processor
0
4
L
0
LFEEH
WRES
ET
19
LT
0
3
0
0xF700
WAKE
CENT
EHLT
UP
18
0
2
0
R/W
⎯
R/W1S
R/W1S
⎯
R/W1S
R/W1S
SURR
EHLT
LOW
PWR
17
0
1
0
TX4939
ENLIN
AUDO
EHLT
16
K
0
0
0
24
24