TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 707

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

CRYPT
26.7. Random Number Generator (RNG) Engine
26.7.1. RNG Registers
NOTE1: In an access to 64 bit register by 32bit instruction, address SWAP function works in write mode but it does not work
NOTE2: Please do not write any data to upper Read Only 32bit field. Because lower 32 bit field would be written by mistake
26.7.1.1. RNG Control and Status Register (RCSR)
26.7.1.2. RNG Parameter Register (RPR)
26.7.1.3. RNG Debug Register (RDR)
Rev. 3.1 November 1, 2005
Offset
C0h
C8h
D0h
D8h
B0h
B8h
in read mode.
by writing data to upper 32 bit field.
Bit(s)
63:4
3
2
1
0
Bit(s)
31:16
15:0
Bit(s)
63:32
31:16
15
14
13:9
Register
RCSR
RPR
RDR
ROR1
ROR2
ROR3
Field
–
R_RST
Field
Field
Rrnerror
Rstrerr
-
R_INTE
R_FIN
R_ST
Lfsrltchtm
Fintm
Rnstcntr
Rdstore
R/W
RO
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
Table 26-20 RNG Control and Status Register (RCSR)
Width
Table 26-21 RNG Parameter Register (RPR)
[63:0]
[31:0]
[63:0]
[63:0]
[63:0]
[63:0]
Table 26-22 RDG Debug Register (RDR)
Default
0
0
0
0
0
Default
0x003F
0x005A
Default
?
?
1
1
0
R / W
Description
Reserved
RNG Interrupt Enable
This bit has to be program before start RNG controller
To clear the interrupt, write “0” to R_INTE bit. Then write “1” back
if there is another RNG operation.
Reset Random Number Generator Controller
After set this bit, need to reset it back to “0” for normal operation
End Signal
After the number of clocks specified by the Rando Number
Output Timing Specify signal (fintm) passes, this signal becomes
active (“1”) and random numbers are output by “R_RN”
RNG Start Bit
This bit will get reset when R_FIN is asserted.
Description
Seed Latch Timing Specify signal
Random Number Output Timing Specify signal
Description
0/1 Balance Value Output signal
Simple Random Number Evaluation Measurement signal
0/1 Balance Error Detection signal
Randomizing Circuit Error Detection signal
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
26-17
0: Disable
1: Enable
0: Normal
1: Reset
0: Normal
1: Done
0: Idle
1: Start
Description
RNG Control and Status Register
RNG Parameter Register
RNG Debug Register
RNG Output Register 1
RNG Output Register 2
RNG Output Register 3
Toshiba RISC Processor
TX4939
26
26