TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 721

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Electrical
28.4.3. DDR SDRAM Interface AC Characteristics
Rev. 3.1 November 1, 2005
(Tc = 0 - 85°C, VDD33 = 3.3 V ± 0.2 V, VDD25 = 2.5 V ± 0.2 V or 2.6 ± 0.1 V, VDDC = 1.25 V ± 0.062 V, VSS = 0 V)
tCK
tCH
tCL
tCKS
tDQSH
tDQSL
tDQS
tDSS
tDSH
tDQSQV
tDQSQIV
t2
t3
Symbol
Note:
1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
11:
12:
13:
14:
† ADDR/CMD = DRA[], DRCS[1:0]*, DRCKP, DRCKM, DRWE*, DRCAS*, DRRAS*, DRCKE
Write cycle timing parameter
The skew consists of pad output skew (+ 250ps) and package routing skew between any two
clock pairs (+ 100ps).
tCKS Timing Parameter, refer to Figure 28-4
The timing consists of pad output skew (+ 250ps) and package routing skew between any
DRCKOUT to any DRDQS (+ 100ps).
tDQS Timing parameter, refer Figure 28-5.
The skew consists of pad output skew (+ 250ps) and package routing skew between any
DRCKOUT to any DRDQS (+ 100ps). Minimum DRDQS pulse width is 45% of DRCKOUT.
tDSS, tDSH timing parameters, refer to Figure 28-6.
During write, DRDQ signals are driven quarter clock earlier such that DRDQS is placed in the
center of data eye window. The skew consists of pad output skew (+ 250ps), package routing
skew between any DRDQS signals and it’s associated DRDQ signals (+ 75ps) and maximum
clock granularity (+ 312.5 ps).
tDQSQV and tDQSQIV timing parameters apply only within DRDQS and its associated DRDQ
signals. Refer to Figure 28-7.
The skew consists of pad output skew (+ 250 ps) and package routing skew (+ 100 ps) between
any DRCKOUT pair to any ADDR/CMD signal. Maximum clock granularity skew is 312.5 ps.
t2 Timing parameter, applies to registered DIMM Environment Only - ADDR/CMD signals are
launched 1/2 clock cycle early. The granularity term does not apply here. Refer to Figure 28-8.
Read cycle timing parameter.
The PDL placement uncertainty is 20%. Package skew between DRDQS and its associated
DRDQs is 75ps. The sum of setup/hold time & receiver uncertainty is 275ps.
t3 timing parameter, refer to Figure 28-9.
DRCKOUT output skew
DRDQS falling edge to DRCKOUT rising edge
DRDQ edge arrival relative to DRDQS
DRCKOUT cycle time
DRCKOUT high pulse width
DRCKOUT low pulse width
DRDQS high pulse width
DRDQS low pulse width
DRCKOUT to DRDQS
DRCKOUT rising edge to DRDQS falling edge
DRDQS to DRDQ shift (when data becomes valid)
DRDQS to DRDQ shift (when data becomes invalid)
ADDR/CMD
†
to DRCKOUT
Parameters
28-5
tDQSHmax -
[0.350+0.2*
tDQSHmin
0.45*tCK
0.45*tCK
0.45*tCK
0.45*tCK
0.45*tCK
0.45*tCK
-{tCK/4 -
(tCK/4)]}
- 0.638}
-0.350
-0.350
0.638}
-0.350
5.000
-{0.5*
Min.
-0.35
-0.35
{0.5*
tDQSHmin +
[0.350+0.2*
tDQSHmax
0.55*tCK
0.55*tCK
0.55*tCK
0.55*tCK
+ 0.638}
(tCK/4)]}
{tCK/4 -
10.000
0.638}
Max.
0.350
0.350
-{0.5*
0.350
{0.5*
-
-
Toshiba RISC Processor
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1
1
1,4,5
1,6,7
1,6,7
1,8,9
1,8,9
1,10,11
12,13,14
Note
TX4939
28
28