TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 85

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Pin Assignment
3.4. Pin Multiplexing
3.4.1. Pin Multiplex for GPIO (Miscellaneous)
PCI Controller has two modes. One is Host mode and the other is Satellite mode. In the Satellite mode, the internal arbiter
cannot be used and external arbiter should be provided. Some of the internal arbiter terminal switched to other signals.
This configuration can be set by CCRG.PCIARB (PCIARB bit in Chip Configuration Register).
Table 3-3 below shows these multiplexing.
3.4.2. Pin Multiplexing for ACLINK and I2S
Rev. 3.1 November 1, 2005
Default Signal Name
ACRESET*
BITCLK
SDIN[0]
SDOUT
SYNC
SDIN[1]
Note 1:
Note 2:
Note 3:
Default Signal Name
GP00
GP01
GP02
GP03
ACRESET*
BITCLK
SDIN[0]
SDOUT
SYNC
SDIN[1]
I2C_CLK
I2C_DO
SPIOUT
SPICS0
SPIIN
SPICLK
REQ[0]*
GNT[0]*
REQ[1]*
GNT[1]*
REQ[2]*
GNT[2]*
REQ[3]*
GNT[3]*
REQ[4]*
GNT[4]*
REQ[5]*
GNT[5]*
Note: All GPIO port is Hiz mode at boot time.
SIO2, 3 are selected by the combinations of SPIMODE, SIO2MODE[1:0], SIO3MODE
bits in Pin Configuration Register (Chapter 7)
I2C function can be selected by setting I2CMODE bit in Pin Configuration Register
(Chapter 7)
GP00 to GP03 are Hiz mode at boot time.
GPIO (Boot Default
GPIO04
GPIO05
GPIO06
GPIO07
GPIO08
GPIO09
GPIO (Boot Default)
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06
GPIO07
GPIO08
GPIO09
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
REQ[0]*
GNT[0]*
REQ[1]*
GNT[1]*
REQ[2]*
GNT[2]*
REQ[3]*
GNT[3]*
REQ[4]*
GNT[4]*
REQ[5]*
GNT[5]*
Table 3-3 GPIO Signal Multiplexing
Table 3-4 I2S Signals
3-13
ACLINK mode
ACRESET*
SDIN[0]
SDOUT
SYNC
SDIN[1]
BITCLK
Function Select or Satellite Mode
Dedicated GPIO
Dedicated GPIO
MCLKA external input/output
MCLKB external input/output
See 3.4.2
See 3.4.2
See 3.4.2
See 3.4.2
See 3.4.2
See 3.4.2
I2C_CLK
I2C_DO
RXD2/ CTS0
TXD2/ RTS0
RXD3 / CIR
TXD3
REQ*
GNT*
INTOUT*
IDSEL
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
I2S 2ch
I2S_WS0
I2S_SCK0
I2S_SD0
I2S_WS1
I2S_SCK1
I2S_SD1
Toshiba RISC Processor
I2S 5.1ch
I2S_ WS
I2S_SCK
I2S_SD0
I2_SD1
--
I2S_SD2
Ball
A15
D14
C14
B14
C18
B17
C17
A18
B18
D17
A17
C16
A16
D15
B16
C15
L2
L3
K1
L4
K4
K3
J3
J2
H2
J4
H4
H3
TX4939
3
3