M25PE20-VMP6TP Numonyx, B.V., M25PE20-VMP6TP Datasheet - Page 47
M25PE20-VMP6TP
Manufacturer Part Number
M25PE20-VMP6TP
Description
1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout
Manufacturer
Numonyx, B.V.
Datasheet
1.M25PE20-VMP6TP.pdf
(64 pages)
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M25PE20, M25PE10
8
9
Reset
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation
(write, program or erase cycle) and data may be lost.
All the Lock bits are reset to ‘0’ after a Reset Low pulse.
Table 14
Table 14.
1.
Initial delivery state
The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte
contains FFh). All usable Status Register bits are 0.
While decoding an instruction
WRDI, RDID, RDSR, READ, RDLR,
Fast_Read, WRLR, PW, PP, PE, SE, BE,
SSE, DP, RDP
Under completion of an Erase or Program
cycle of a PW, PP, PE, SSE, SE, BE
operation
Under completion of a WRSR operation
Device deselected (S High) and in Standby
mode
S remains Low while Reset is Low.
shows the status of the device after a Reset Low pulse.
Reset pulse occurred
Device status after a Reset Low pulse
Conditions:
(1)
: WREN,
Lock bits status
Reset to ‘0’
Reset to ‘0’
Reset to ‘0’
Reset to ‘0’
POR (after t
Same as POR
Same as POR
Internal logic
Equivalent to
Equivalent to
status
POR
W
)
could be modified
Addressed data
Write is correctly
Addressed data
Not significant
Not significant
completed
Reset
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