RM7000 PMC-Sierra, Inc., RM7000 Datasheet - Page 16

• Manufacturer Part Number: RM7000
• Description: RM7000 Microprocessor with On-Chip Secondary Cache Datasheet Released
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
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algorithms allowing the RM7000 to eliminate the need for a separate DSP engine in many
embedded applications.
By pipelining the multiply-accumulate function and dynamically determining the size of the input
operands, the RM7000 is able to maximize throughput while still using an area efficient
implementation.
Floating-Point Coprocessor
The RM7000 incorporates a high-performance fully pipelined floating-point coprocessor which
includes a floating-point register file and autonomous execution units for multiply/add/convert and
divide/square root. The floating-point coprocessor is a tightly coupled co-execution unit, decoding
and executing instructions in parallel with, and in the case of floating-point loads and stores, in
cooperation with the M pipe of the integer unit. As described earlier, the superscalar capabilities of
the RM7000 allow floating-point computation instructions to issue concurrently with integer
instructions.
Floating-Point Unit
The RM7000 floating-point execution unit supports single and double precision arithmetic, as
specified in the IEEE Standard 754. The execution unit is broken into a separate divide/square root
unit and a pipelined multiply/add unit. Overlap of divide/square root and multiply/add is
supported.
The RM7000 maintains fully precise floating-point exceptions while allowing both overlapped
and pipelined operations. Precise exceptions are extremely important in object-oriented
programming environments and highly desirable for debugging in any environment.
The floating-point unit’s operation set includes floating-point add, subtract, multiply, multiply-
add, divide, square root, reciprocal, reciprocal square root, conditional moves, conversion between
fixed-point and floating-point format, conversion between floating-point formats, and floating-
point compare. Table 5 gives the latencies of the floating-point instructions in internal processor
cycles.
Floating-Point General Register File
The floating-point general register file, FGR, is made up of thirty-two 64-bit registers. With the
floating-point load and store double instructions, LDC1 and SDC1 , the floating-point unit can
take advantage of the 64-bit wide data cache and issue a floating-point coprocessor load or store
doubleword instruction in every cycle.
The floating-point control register file contains two registers; one for determining configuration
and revision information for the coprocessor and one for control and status information. These
registers are primarily used for diagnostic software, exception handling, state saving and restoring,
and control of rounding modes.
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Released
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