RM7000 PMC-Sierra, Inc., RM7000 Datasheet - Page 28

• Manufacturer Part Number: RM7000
• Description: RM7000 Microprocessor with On-Chip Secondary Cache Datasheet Released
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
4.26 System Address/Data Bus
4.27 System Command Bus
4.28 Handshake Signals
Figure 8 Typical Embedded System Block Diagram
The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the
RM7000 and the rest of the system. It is protected with an 8-bit parity check bus, SysADC.
The system interface is configurable to allow easy interfacing to memory and I/O systems of
varying frequencies. The data rate and the bus frequency at which the RM7000 transmits data to
the system interface are programmable via boot time mode control bits. Also, the rate at which the
processor receives data is fully controlled by the external device. Therefore, either a low cost
interface requiring no read or write buffering or a faster, high-performance interface can be
designed to communicate with the RM7000. Again, the system designer has the flexibility to make
these price/performance trade-offs.
The RM7000 interface has a 9-bit System Command (SysCmd) bus. The command bus indicates
whether the SysAD bus carries an address or data. If the SysAD bus carries an address, then the
SysCmd bus also indicates what type of transaction is to take place (for example, a read or write).
If the SysAD bus carries data, then the SysCmd bus also gives information about the data (for
example, this is the last data word transmitted, or the data contains an error). The SysCmd bus is
bidirectional to support both processor requests and external requests to the RM7000. Processor
requests are initiated by the RM7000 and responded to by an external device. External requests are
issued by an external device and require the RM7000 to respond.
The RM7000 supports one to eight byte and 32-byte block transfers on the SysAD bus. In the case
of a sub-doubleword transfer, the 3 low-order address bits give the byte address of the transfer, and
the SysCmd bus indicates the number of bytes being transferred.
There are ten handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are
used by an external device to indicate to the RM7000 whether it can accept a new read or write
RM7000
TcLine, etc.
Tertiary Cache
(optional)
DRAM
Latch
72
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
SysCmd
72
72
SysAD Bus
72
25
Flash/
ROM
Boot
8
Memory I/O
Controller
Address
Control
x
PCI Bus
x
Released
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