RM7000 PMC-Sierra, Inc., RM7000 Datasheet - Page 37

• Manufacturer Part Number: RM7000
• Description: RM7000 Microprocessor with On-Chip Secondary Cache Datasheet Released
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
4.36 Standby Mode
4.37 JTAG Interface
4.38 Boot-Time Options
4.39 Boot-Time Modes
Table 15 Interrupt Vector Spacing
The RM7000 provides a means to reduce the amount of power consumed by the internal core
when the CPU would not otherwise be performing any useful operations. This state is known as
Standby Mode.
Executing the WAIT instruction enables interrupts and enters Standby Mode. When the WAIT
instruction completes the W pipe stage, if the SysAD bus is currently idle, the internal processor
clocks will stop thereby freezing the pipeline. The phase lock loop, or PLL, internal timer/counter,
and the “wake up” input pins: INT[9:0]*, NMI*, ExtReq*, Reset*, and ColdReset* continue to
operate in their normal fashion. If the SysAD bus is not idle when the WAIT instruction completes
the W pipe stage, then the WAIT is treated as a NOP . Once the processor is in Standby, any
interrupt, including the internally generated timer interrupt, will cause the processor to exit
Standby and resume operation where it left off. The WAIT instruction is typically inserted in the
idle loop of the operating system or real time executive.
The RM7000 interface supports JTAG boundary scan in conformance with IEEE 1149.1. The
JTAG interface is especially helpful for checking the integrity of the processor’s pin connections.
Fundamental operational modes for the processor are initialized by the boot-time mode control
interface. The boot-time mode control interface is a serial interface operating at a very low
frequency (SysClock divided by 256). The low frequency operation allows the initialization
information to be kept in a low cost EPROM; alternatively the twenty or so bits could be generated
by the system interface ASIC.
Immediately after the VccOK signal is asserted, the processor reads a serial bit stream of 256 bits
to initialize all the fundamental operational modes. ModeClock runs continuously from the
assertion of VccOK.
The boot-time serial mode stream is defined in Table 16. Bit 0 is the bit presented to the processor
when
ICR[4..0]
0x0
0x1
0x2
0x4
0x8
0x10
others
VccOK
is de-asserted; bit 255 is the last.
Spacing
0x000
0x020
0x040
0x080
0x100
0x200
reserved
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Released
37