RM7000 PMC-Sierra, Inc., RM7000 Datasheet - Page 9

• Manufacturer Part Number: RM7000
• Description: RM7000 Microprocessor with On-Chip Secondary Cache Datasheet Released
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
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Features
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Dual Issue symmetric superscalar microprocessor with instruction prefetch optimized for
system level price/performance
High-performance system interface
Integrated primary and secondary caches — all are 4-way set associative with 32 byte line size
Integrated external cache controller (up to 8 MB)
High-performance floating-point unit — 600 MFLOPS maximum
MIPS IV Superset Instruction Set Architecture
Integrated memory management unit
Embedded application enhancements
Fully static CMOS design with dynamic power down logic
RM5271 pin compatible, 304 pin TBGA package, 31x31 mm
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200, 250, 266, 300 MHz operating frequency
>500 Dhrystone 2.1 MIPS @ 300 MHz
1000 MB per second peak throughput
125 MHz max. freq., multiplexed address/data
Supports two outstanding reads with out-of-order return
Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
16 KB instruction, 16 KB data, 256 KB on-chip secondary
Per line cache locking in primaries and secondary
Fast Packet Cache™ increases system efficiency in
networking applications
Single cycle repeat rate for common single-precision operations and some double-pre-
cision operations
Single cycle repeat rate for single-precision combined multiply-add operations
Two cycle repeat rate for double-precision multiply and double-precision combined
multiply-add operations
Data PREFETCH instruction allows the processor to overlap cache miss latency and
instruction execution
Single-cycle floating-point multiply-add
Fully associative joint TLB (shared by I and D translations)
64/48 dual entries map 128/96 pages
Variable page size
Specialized DSP integer Multiply-Accumulate instructions, ( MAD / MADU ) and three-
operand multiply instruction ( MUL )
I&D Test/Break-point (Watch) registers for emulation & debug
Performance counter for system and software tuning & debug
Fourteen fully prioritized vectored interrupts - 10 external, 2 internal, 2 software
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Released
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