STPCC4 STMicroelectronics, STPCC4 Datasheet - Page 64

• Manufacturer Part Number: STPCC4
• Description: STPC CONSUMER-II DATASHEET - X86 CORE PC COMPATIBLE INFORMATION APPLIANCE SYSTEM-ON-CHIP
• Manufacturer: STMicroelectronics

DESIGN GUIDELINES
6.2. STPC CONFIGURATION
The STPC is a very flexible product thanks to
decoupled clock domains and to strap options
enabling a user-optimized configuration.
As some trade off are often necessary, it is
important to do an analysis of the application
needs prior to design a system based on this
product. The applicative constraints are usually
the following:
Some other elements can help to tune the choice:
On the STPC side, the configurable parameters
are the following:
6.2.1. LOCAL BUS / ISA BUS
The selection between the ISA bus and the Local
Bus is relatively simple. The first one is a standard
bus but slow. The Local Bus is fast and
programmable but doesn’t support any DMA nor
external master mechanisms. The Table 6-1
below summarize the selection:
Before implementing a function requiring DMA
capability on the ISA bus, it is recommended to
check if it exists on PCI, or if it can be
implemented differently, in order to use the local
bus mode.
6.2.2. CLOCK CONFIGURATION
The CPU clock and the memory clock are
independent unless the ”synchronous mode”
strap option is set (see the STRAP OPTIONS
chapter). The potential clock configurations are
then relatively limited as listed inTable 6-2.
64/93
Legacy I/O device (Floppy, ...), Super I/O
DMA capability (Soundblaster)
Flash, SRAM, basic I/O device
Fast boot
Boot flash of 4MB or more
Programmable Chip Select
- CPU performance
- graphics / video performances
- power consumption
- PCI bandwidth
- booting time
- EMC
- Code size of CPU Consuming tasks
- Data size and location
- synchronous / asynchronous mode
- HCLK speed
- MCLK speed
- CPU clock ratio (x1, x2)
- Local Bus / ISA bus
Table 6-1. Bus mode selection
Need
Release 1.5 - January 29, 2002
Selection
Local Bus
Local Bus
Local Bus
Local Bus
ISA Bus
ISA Bus
The
compared to the asynchronous mode is a lower
latency when accessing SDRAM from the CPU or
the PCI (saves 4 MCLK cycles for the first access
of the burst). For the same CPU to Memory
transfer performance, MCLK as to be roughly
higher by 20MHz between SYNC and ASYNC
modes (example:
ASYNC).
In all cases, use SDRAM with CAS Latency
equals to 2 (CL2) for the best performances.
The advantage of the asynchronous mode is the
capability to reprogram the MCLK speed on the
fly. This could help for applications were power
consumption must be optimized.
Regarding PCI bandwidth, the best is to have
HCLK at 100MHz as it gives twice the bandwidth
compared to HCLK at 66MHz.
The last, and more complex, information to
consider is the behaviour of the software. In case
high CPU or FPU computation is needed, it is
sometime better to be in DX2-133/MCLK=66
synchronous mode than DX2-133/MCLK=100
asynchronous mode. This depends on the locality
of the number crunching code and the amount of
data manipulated.
The Table 6-3 below gives some examples. The
right column correspond to the configuration
number as described in Table 6-2:
Obviously, the values for HCLK or MCLK can be
reduced compared toTable 6-2 in case there is no
need to push the device at its limits, or when
avoiding to use specific frequency ranges (FM
radio band for example).
Need CPU power
Critical code fits into L1 cache
Need CPU power
Code or data does not fit into L1 cache
Need high PCI bandwitdh
Need flexible SDRAM speed
C
1
2
3
Asynchronous
Synchronous
Synchronous
advantage
Table 6-3. Clock mode selection
Mode
Table 6-2. Main STPC modes
Constraints
of the synchronous
HCLK
66MHz SYNC = 96MHz
MHz
100
66
66
CPU clock
clock ratio
133 (x2)
133 (x2)
100 (x1)
MCLK
MHz
100
100
66
mode
C
1
3
3
2