MSAN-141 Zarlink Semiconductor, Inc., MSAN-141 Datasheet - Page 14

• Manufacturer Part Number: MSAN-141
• Description: Implementation Details of the MT8930B-31B S-T Interface
• Manufacturer: Zarlink Semiconductor, Inc.

MSAN-141
channels on the ST-BUS can be mapped into either
half of the S-Bus frame. For this reason, a HALF
signal is required to identify the source or destination
of the ST-BUS channels on the S-Bus frame. Figure
3 reveals the frame mapping between the ST-BUS
system interface and the S-Bus line port for both the
NT and TE simultaneously under zero line length
condition.
3.3.1
Figure 3 reveals the functional timing diagram which
uses shading to identify the ST-BUS frame mapping
into the S-Bus for both the transmission of NT and
TE frames (at zero line length). Although the diagram
is split into separate sections, the phase relationship
between NT and TE frames cannot be ignored.
For the NT transmit S-Bus frame, the ST-BUS
mapping is dependent on the state of the HALF
signal as input during frame pulse. If HALF=1, the
ST-BUS frame being received on DSTi is transmitted
on the second half of the current S-Bus frame. (This
implies that the M/S-bit of the C-channel control
register will be mapped into the S-bit). If HALF=0,
the ST-BUS frame being received on DSTi is
transmitted in the first half of the next S-Bus frame.
(This implies that the M/S-bit of the C-channel
control register will be mapped into the M-bit). If the
HALF pin is tied to V
signal will establish the mapping of the ST-BUS on to
the S-Bus frame. A transition on the HALF pin will
overrule the internal signal and cause the S-Bus
frame to be repositioned accordingly. (This HALF
signal can also be accessed using B2 of the NT
mode C-channel Control Register.)
The information being transmitted from the NT, is
received by the TE and is output to the ST-BUS with
a delay of a little more than a couple of bits. This can
be seen in the diagram where the received B- and D-
channels are output on the ST-BUS frame following
the reception of this data on the S-Bus port. Any
delay introduced from the transmission line will be
added to this throughput delay.
For the TE transmit S-Bus frame, data mapping of
the ST-BUS to S-Bus frame is again relevant to the
state of the output on the HALF pin (sampled on the
falling edge of the C4b clock within the frame pulse
low window), or the HALF bit in the Status Register.
When HALF=1, information on DSTi will be routed to
the second half of the S-Bus frame. (Since the F0b
pulse occurs at the S-Bus frame boundary, the
transmit throughput delay is a minimum of 125 s.)
Conversely, if HALF=0, the information on DSTi will
be routed to the first half of the S-Bus frame.
A-214
Frame Mapping
DD
or V
SS
, an internal HALF
With zero line length, the transmission delay for the
TE transmit S-Bus frame will have a nominal delay of
two 192 kbit/s bit periods relative to the NT transmit
S-Bus frame. (This is seen by lining up the NT
transmit and TE transmit S-Bus frames relative to the
TE ST-BUS frame pulse.) The S-Bus frame is
received on the NT and is output on the ST-BUS
(DSTo) with the delay shown in Figure 3.
Using Figure 3, the end-to-end delay introduced by
the interfaces (at zero line length) can be calculated
as follows:
1. From the NT, a channel under test will experience
2. The delay from the TE DSTi to the NT DSTo of
This yields a total end-to-end throughput delay with
zero line length of 500 s.
3.3.2
As mentioned earlier, the SNIC uses the first four ST-
BUS channels following the framing pulse to carry
the D, C and two B-channels. Under normal
operation, the two B-channels from the ST-BUS will
be transmitted and received on the S-Bus while the
D-channel will be transmitted/received from the
FIFOs of the HDLC formatter. If the D-channel is to
be sourced externally, the HDLC formatter can be
bypassed which will provide a 16 kbit/s data path
(two least significant bits of the 64 kbit/s channel)
from the ST-BUS to S-Bus and vice-versa. The
HDLC formatter is bypassed by disabling both the
HDLC transmitter and receiver (B6 and B7 and the
HDLC Control Register 1 are set to”0”).
If the D-channel requires more bandwidth, the DinB
feature can be set in the SNIC (B5 of C-channel
Control Register) which will place the 64 kbit/s D-
channel in the B1 timeslot. This has the effect of
replacing the B1-channel on the S-Bus with the
active 64 kbit/s D-channel received on the ST-BUS
input. With the DinB option active, the 16 kbit/s D-
channel on the S-Bus will be placed in an idle mode
and cannot be accessed until the function is
disabled.
delay from the NT DSTi to the TE DSTo of
approximately 208.33 s, (i.e., 1 X 125 s + 16
X 1/192kbit/s).
approximately 292
1/192kbit/s).
Channel Mapping
s, (i.e., 2 X 125
Application Note
s + 8 X