CS61582-IQ5R Cirrus Logic, Inc., CS61582-IQ5R Datasheet
CS61582-IQ5R
Related parts for CS61582-IQ5R
CS61582-IQ5R Summary of contents
Page 1
... Crystal Semiconductor Corporation P. O. Box 17847, Austin, Texas, 78760 (512) 445 7222 FAX:(512) 445 7581 General Description The CS61582 is a dual line interface optimized for highly-integrated T1/E1 asynchronous or synchronous multiplexer applications such as SONET and SDH. Each channel features individual control and status pins which eliminates the need for external microproc- essor support ...
Page 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
ABSOLUTE MAXIMUM RATINGS Parameter DC Supply (TV+1, TV+2, RV+1, RV+2, AV+, DV+) (Note 1) Input Voltage (Any Pin) Input Current (Any Pin) Ambient Operating Temperature Storage Temperature WARNING: Operations at or beyond these limits may result in permanent damage to ...
Page 4
DIGITAL CHARACTERISTICS Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Digital pins) I OUT = -40 A Low-Level Output Voltage (Digital pins) I OUT = 1.6 mA Input Leakage Current (Digital pins except J-TMS, and J-TDI) Notes: 7. ...
Page 5
ANALOG SPECIFICATIONS Parameter Transmitter AMI Output Pulse Amplitudes E1, 75 E1, 120 T1, DSX-1 Recommended Transmitter Output Load T1 E1, 75 E1, 120 Jitter Added During kHz Remote Loopback 8 kHz - 40 kHz 10 Hz ...
Page 6
SWITCHING CHARACTERISTICS - T1 CLOCK/DATA pins within 5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3) Parameter TCLK Frequency TCLK Duty Cycle RCLK Duty Cycle Rise Time (All Digital Outputs) Fall ...
Page 7
Any Digital Output RCLK (CLKE = 1) RPOS RNEG RCLK (CLKE =0) Figure 2. Recovered Clock and Data Switching Characteristics Figure 3. Transmit Clock and Data Switching Characteristics DS224PP1 t r 90% 10% Figure 1. Signal Rise and Fall Characteristics ...
Page 8
SWITCHING CHARACTERISTICS - JTAG TV+, RV+ = nominal 0.3V; Inputs: Logic 0 = 0V, Logic 1 = RV+) Parameter Cycle Time J-TMS/J-TDI to J-TCK rising setup time J-TCK rising to J-TMS/J-TDI hold time J-TCK falling to J-TDO valid J-T C ...
Page 9
... Table 1. Typical output pulses are shown in Figures 5 and 6. These pulse shapes are fully pre-defined by circuitry in the CS61582, and are fully compli- ant with appropriate standards when used with our application guidelines in standard installations. Both channels must be operated at the same line rate (both T1 or both E1) ...
Page 10
... The CS61582 driver will automatically detect an inactive TLCK input (i.e., no valid data is being clocked to the driver). When this condition is de- tected, the driver is forced low (except during ...
Page 11
... Falling comes the frequency of the reference clock. REFERENCE CLOCK The CS61582 requires a reference clock with a minimum accuracy of applications. This clock can be either a 1X clock (i.e., 1.544 MHz or 2.048 MHz), or can clock (i.e., 12.352 MHz or 16.384 MHz) as se- ...
Page 12
... REFCLK and TCLK are present. The power-up reset performs the same functions as the RESET pin. LINE CONTROL AND MONITORING Line control and monitoring of the CS61582 is achieved using the control pins. The controls and indications available on the CS61582 are de- tailed below. ...
Page 13
... This verification is sup- ported by the ability to externally set the signals on the digital output pins of the CS61582, and to externally read the signals present on the input pins of the CS61582. Additionally, the manufac- turer ID, part number and revision of the CS61582 can be read during board test using JTAG boundary scan ...
Page 14
... Device Identification Register: The DIR provides input the manufacturer, part number, and version of the input CS61582. This information can be used to verify that the proper version or revision number has been used in the system under test. The DIR is 32 bits long and is partitioned as shown in figure 10. ...
Page 15
... EXTEST connects the BSR to the J-TDI and J-TDO pins. The normal path be- tween the CS61582 logic and I/O pins is broken. The signals on the output pins are loaded from the BSR and the signals on the input pins are loaded into the BSR ...
Page 16
... J-TMS at each rising edge of J-TCK. Test-Logic-Reset State In this state, the test logic is disabled to continue normal operation of the device. During initiali- zation, the CS61582 initializes the instruction register with the IDCODE instruction. Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the J-TMS input is held high for at least five rising edges of J-TCK ...
Page 17
Shift-DR State In this controller state, the test data register con- nected between J-TDI and J-TDO as a result of the current instruction shifts data on stage to- ward its serial output on each rising edge of J-TCK. The instruction ...
Page 18
Capture-IR State In this controller state, the shift register con- tained in the instruction register loads a fixed value of "01" on the rising edge of J-TCK. This supports fault-isolation of the board-level serial test data path. Data registers selected ...
Page 19
TCK TMS Controller state TDI Parallel Input shift-register Parallel output of IR Parallel Input to TDR Parallel output of TDR TDR shift-register Register selected TDO enable Inactive TDO DS224PP1 IDCODE Instruction register Act Inactive = Don't care ...
Page 20
TCK TMS Controller state TDI Parallel Input shift-register Parallel output of IR Parallel Input to TDR TDR shift-register Parallel output of TDR Register Selected TDO enable Inactive TDO 20 Instruction Old data Test data register Active Inactive ...
Page 21
... TGND1 TRING1 MRING1 MTIP1 RTIP1 RRING1 RV+1 RGND1 AGND1 BGREF AGND2 AV+ DS224PP1 CS61582 DV+ DGND3 CON02 CON11 CON12 CON21 CON22 DPM2 RCLK2 ...
Page 22
Power Supplies AGND1, AGND2 : Analog Ground (Pins 21, 23) Analog supply ground pins. AV+ : Analog Power Supply (Pin 24) Analog supply pin for the internal bandgap reference and timing generation circuits. BGREF : Bandgap Reference (Pin 22) This ...
Page 23
TCLK1, TCLK2 : Transmit Clock (Pins 4, 45) TPOS1, TPOS2 : Transmit Positive Data (Pins 5, 44) TNEG1, TNEG2 : Transmit Negative Data (Pins 6, 43) The transmit clock and data are input on these pins. The signal is driven ...
Page 24
RLOOP1, RLOOP2 : Remote Loopback (Pins 63, 27) A remote loopback is selected when RLOOP is high. The data received from the line interface at RTIP and RRING is looped back through the jitter attenuator and retransmitted on TTIP and ...
Page 25
PHYSICAL DIMENSIONS DS224PP1 Terminal Detail 1 64-Pin TQFP MILLIMETERS INCHES MIN MAX MIN DIM - 1. 0.00 A 0.00 1 0.006 0.14 0.26 B ...
Page 26
... The 0.47 F capacitor to ground provides the necessary differential input voltage reference for the receiver. Power Supply As shown in Figure A1, the CS61582 operates from a 5.0 Volt supply. Separate analog and digi- tal power supply and ground pins provide internal isolation. The TGND, RGND, and DGND ground pins must not be more negative than AGND ...
Page 27
... REFCLK pin. The oscillator must have a minimum symme- try of 40-60% and minimum stability of ppm for T1 and E1 applications. Based on these specifications, some suggested crystal oscillators for use with the CS61582 are shown in Table Manufacturer Part Number Comclok CT31CH ...
Page 28
Turns Ratio Manufacturer 1:1.15 Pulse Engineering 28 Part Number PE-65388 PE-65770 PE-65838 PE-68674 PE-65870 Schott 67124840 Valor ST5112 Table A4. Recommended Transformers Schematic & Layout Review Service ...
Page 29
Notes • ...
Page 30
Notes • ...
Page 31
Notes • ...
Page 32
TM Smart Analog is a Trademark of Crystal Semiconductor Corporation ...