PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 309
PM5380-BI
Manufacturer Part Number
PM5380-BI
Description
Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM5380-BI.pdf
(440 pages)
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Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
Register 0x1008: APS Reset Control
When the interrupt output INTB goes low, this register allows the source of the active interrupt
to be identified down to the block level for the APS interfaces. Further register accesses are
required for the block in question to determine the cause of an active interrupt and to
acknowledge the interrupt source..
TXAPRST[1:0]:
RXAPRST[1:0]:
Reserved:
The TXAPRST[1:0] bits allow the transmit APS serial interfaces to be reset under software
control. If the TXAPRST[x] bit is a logic one, the associated transmit APS interface (TAOP
and associated logic) is held in reset. This bit is not self-clearing. Therefore, a logic zero
must be written to bring the channel out of reset.
Holding the channel in a reset state places it into a low power, stand-by mode. A hardware
reset or top level reset using RESET clears the TXAPSRST[1:0] bits, thus negating the
software reset. Otherwise, the effect of the software reset is equivalent to that of a hardware
reset. Reseting transmit APS interface #0 (TXAPRST[0] is set high) may cause the other
link to switch to a new A1/A2 frame alignment. This will cause an out-of-frame (OOF)
failure across all APS interfaces.
The RXAPRST[1:0] bits allow the receive APS serial interfaces to be reset under software
control. If the RXAPRST[x] bit is a logic one, the associated recieve APS interface (RAOP,
RAPS and associated logic) is held in reset. This bit is not self-clearing. Therefore, a logic
zero must be written to bring the channel out of reset.
Holding the channel in a reset state places it into a low power, stand-by mode. A hardware
reset or top level reset using RESET clears the RXAPSRST[1:0] bits, thus negating the
software reset. Otherwise, the effect of the software reset is equivalent to that of a hardware
reset.
The reserved bits must be programmed to ‘1’ for proper operation.
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
Reserved
RXAPRST[1]
RXAPRST[0]
Reserved
Reserved
TXAPRST[1]
TXAPRST[0]
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Default
0
0
0
0
0
0
0
0
Released
309
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