PM8621 PMC-Sierra, Inc., PM8621 Datasheet - Page 165

• Manufacturer Part Number: PM8621
• Description: NSE-8G Standard Product Data Sheet Preliminary
• Manufacturer: PMC-Sierra, Inc.

12.14.1 TAP Controller
12.14.2 States
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary
input, TCK. All state transitions are controlled using primary input, TMS. The finite state
machine is described below.
Figure 35 TAP Controller Finite State Machine
Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in normal mode
operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered
synchronously regardless of the current TAP controller state by forcing input, TMS high for 5
TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction.
0
1
Test-Logic-Reset
Run-Test-Idle
TRSTB=0
0
1
1
0
Select-DR-Scan
Capture-DR
Update-DR
Pause-DR
Exit1-DR
Exit2-DR
Shift-DR
1
1
1
0
0
0
1
0
All transitions dependent on input TMS
0
0
1
1
NSE-8G™ Standard Product Data Sheet
1
0
Select-IR-Scan
Capture-IR
Update-IR
Pause-IR
Exit1-IR
Exit2-IR
Shift-IR
1
1
1
0
0
0
1
0
0
0
1
1
Preliminary
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