WM8522 Wolfson Microelectronics plc, WM8522 Datasheet - Page 32

• Manufacturer Part Number: WM8522
• Description: 24-bit, 192khz 6-channel Dac With 1.7vrms Line Driver
• Manufacturer: Wolfson Microelectronics plc

WM8522
w
(all channels)
Attenuation
Attenuation
Attenuation
REGISTER
Attenuation
Attenuation
ADDRESS
DAC Mute
DACR3
DACL3
DACR2
DACL2
Master
Digital
Digital
Digital
Digital
Digital
(06h)
(07h)
(08h)
(09h)
(04h)
(05h)
R6
R7
R8
R9
R4
R5
2:1
5:3
BIT
7:0
7:0
7:0
7:0
7:0
5:4
8:6
0
8
8
8
8
8
2
3
DZFM[1:0]
RDA2[7:0]
RDA3[7:0]
LDA2[7:0]
LDA3[7:0]
MASTDA
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
IWL[5:4]
DMUTE
PHASE
LABEL
ZCD
[7:0]
[2:0]
BCP
LRP
[8:6]
Not latched
Not latched
Not latched
Not latched
Not latched
DEFAULT
11111111
11111111
11111111
11111111
11111111
(0dB)
(0dB)
(0dB)
(0dB)
(0dB)
000
000
00
00
0
0
0
In left/right/I
LRCLK Polarity (normal)
In DSP Mode:
BCLK Polarity (DSP Modes):
Input Word Length:
Bit
0
1
2
Digital Attenuation data for Left channel DACL2 in 0.5dB steps. See
Table 16
Controls simultaneous update of all Attenuation Latches
Digital Attenuation data for Right channel DACR2 in 0.5dB steps.
Controls simultaneous update of all Attenuation Latches
Digital Attenuation data for Left channel DACL3 in 0.5dB steps. See
Controls simultaneous update of all Attenuation Latches
Digital Attenuation data for Right channel DACR3 in 0.5dB steps.
Controls simultaneous update of all Attenuation Latches
Digital Attenuation data for all DAC channels in 0.5dB steps. See
Controls simultaneous update of all Attenuation Latches
DAC Digital Volume Zero Cross Enable:
Zero flag/mute decode. See Table 11, Table 12 and Table 13 for
details.
DAC Soft Mute Select. See Table 10 for details.
0: Store LDA2 in intermediate latch (no change to output)
1: Store LDA2 and update attenuation on all channels.
See Table 16
0: Store RDA2 in intermediate latch (no change to output)
1: Store RDA2 and update attenuation on all channels.
Table 16
0: Store LDA3 in intermediate latch (no change to output)
1: Store LDA3 and update attenuation on all channels.
See Table 16
0: Store RDA3 in intermediate latch (no change to output)
1: Store RDA3 and update attenuation on all channels.
Table 16
0: Store gain in intermediate latch (no change to output)
1: Store gain and update attenuation on all channels.
0: Normal BCLK polarity
1: Inverted BCLK polarity
00 : 16 bit data
01: 20 bit data
10: 24 bit data
11: 32 bit data
0 : Normal LRCLK polarity
1: Inverted LRCLK polarity
0 : DSP mode A
1: DSP mode B
0: Zero cross detect enabled
1: Zero cross detect disabled
2
S Modes:
DAC
DAC1L/R
DAC2L/R
DAC3L/R
DESCRIPTION
Phase
1 = invert
1 = invert
1 = invert
PD, Rev 4.1, July 2009
Production Data
32