MTC50150 STMicroelectronics, MTC50150 Datasheet - Page 10

• Manufacturer Part Number: MTC50150
• Description: Adsl Gateway Processor
• Manufacturer: STMicroelectronics

MTC50150
Table 2. MTC50150 Pin list (continued)
10/20
SD_DQM2
SD_DQM3
ARMDEBUG
FLASHBOOT /
PLL_CTR_RUN
BYPASSPLL /
FS IN #15
UTOPIASEL
TCK
TDI
TDO
TMS
NTRST
ISA_nCS /
TRACEPORT9 /
U_NOTRXREF
ISA_nRD
ISA_nWR
ROM_nCS
ROM_ADDR21 /
PLL_DIV_OUT/
TRACEPKT11 /
U_RXSOC
ROM_ADDR20 /
PLL_NOM_OUT /
TRACEPKT10 /
U_RXCLAV
ROM_ADDR19 /
TRACEPKT9 /
U_TXCLAV
Name
R13
H15
C13
D14
B13
A14
E15
E16
Pin
P7
N7
B7
A7
C5
E3
F3
E1
E4
F4
ARM/Miscellaneous Interface (4)
OZ
O /
O /
O /
OZ
O /
O /
O /
OZ
O /
O /
OZ
ID
IU
IU
IU
ID
I /
B
O
O
O
O
O
O
I
I
I
JTAG/Test Interface (5)
ISA-like Interface (42 )
Buffer Type
PRT08DGZ
PRT08DGZ
PDUWDGZ
PDUWDGZ
PRT08DGZ
PDUWDGZ
PRT08DGZ
PRT08DGZ
PRT08DGZ
PRT08DGZ
PRT08DGZ
PRT08DGZ
PRT08DGZ
PDDWDGZ
PDDWDGZ
PDIDGZ
PDIDGZ
PDIDGZ
SDRAM Data Mask 2 (Byte Enable)
SDRAM Data Mask 3 (Byte Enable)
ARM Debug Test mode (multiplexes the
ARM TAP onto the JTAG pins)
Tied to ‘0’ in functional mode
Boot from external Flash PROM rather
than from internal ROM
Starts/Stops the PLL test counter
Tied to ‘1’ in functional mode
Bypass CPU clock generation PLL
Tied to ‘0’ in functional mode
Full scan input chain 15 (ARM946E)
Select external Utopia Interface of ADSL
core (Sachem_ip)
Boundary ScanTest Clock
Boundary Scan Test Data In
Boundary Scan Test Data Out
Boundary Scan Test Mode Shift
Boundary Scan Reset
ISA bus Chip Select / Address Enable /
ETM9 Trace port 9 /
Utopia Receive Reference Clock
ISA bus Read Strobe / Output Enable
ISA bus Write Strobe
Flash PROM Chip Select / Address
Enable
Flash PROM Address Bit 21 /
Divided clock in PLL test mode /
ETM9 Trace packet 11 /
Utopia Receive Start Of Cell
Flash PROM Address Bit 20 /
PLL output clock in PLL test mode/
ETM9 Trace packet 10 /
Utopia Receive Cell Available
Flash PROM Address Bit 19 /
ETM9 Trace packet 9 /
Utopia Transmit Cell Available
Description