SPFMOR302 Avago Technologies, SPFMOR302 Datasheet - Page 5

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SPFMOR302

Manufacturer Part Number
SPFMOR302
Description
Plastic Fiber Optic Receiver For Most
Manufacturer
Avago Technologies
Datasheet
Design & Layout rules
Layout example
The reference board from OASIS Silicon Systems follows the requirements above. The schematic is very similar to the
example above, but does not include the connection to the power supply, the OS8104 or the micro controller.
The examples below for top- and bottom layer is the layout of the reference design board and shows how the layout
around the optical receiver and transmitter should look like.
It is strongly recommended to follow these examples in your design to get best performance!
Note:
1. The buffer circuit (IC1), the connectors and jumpers in the middle to the right section of the schematic are only for being used together with the
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The 100nF bypass capacitors of the FOTs must be located as close as possible between the pins V
FOTs. Use ceramic caps and tantalum caps with low ESR.
Also the inductor/ ferrite bead (receiver) and the -3dB - control circuit (transmitter) must be placed as close as
possible to the FOTs. We prefer ferrite beads (e.g. type 74279214 Würth Elektronik) since the D.C. resistance is very
low. In case other inductors are used, the D.C. resistance should be less than 3Ohm.
For EMC, a ferrite bead should be connected to the power supply, close to the transmitter and the receiver. Do not
use only one ferrite bead together for receiver and transmitter!
For the ground connection a ground plane is recommended (Y-structure). That means the ground planes of the
transmitter, the receiver and the shielding must be separated. The three ground planes should be connected
together behind the bypass capacitors (refer to the PCB design below). This ground signal should be connected
directly to the ground plane of the MOST controller (e.g. OS8104) and the power supply on the top layer and/or
bottom layer and ground layer as it is indicated in the example below.
If a multi layer design is used the ground layer must have the same ground separation like shown for the top layer!
A serial resistor in the Rx/ Tx data line will also reduce EMC - problems. For Rx the resistor must be placed near the
receiver - for Tx the resistor must be placed near the MOST controller chip. The value depends on the distance
between the FOTs and the MOST chip (< 5cm) and can be within a range up to 150R. Higher values for the resistors
will increase jitter and can therefore cause locking problems of the MOST PLL!
The Rx/ Tx signals should not be routed in parallel over a long distance, but may be embedded with ground copper,
if possible.
The GND pin and the pin of R
should be a good connection to the PCB - no isolation gaps! Both pins should dip into a copper area (see layout
example below).
reference board, and will not be necessary for your hardware design.
ext
(15K - resistor) of the transmitter are used for heat dissipation. Therefore there
CC
and GND of the

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