PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 102

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.64 PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h
7.5.65 DOWNSTREAM MEMORY 0 TRANSLATED BASE REGISTER – OFFSET 98h
7.5.66 DOWNSTREAM MEMORY 0 SETUP REGISTER – OFFSET 9Ch
Pericom Semiconductor
BIT
8
12:9
14:13
15
BIT
21:16
22
23
31:24
BIT
11:0
31:12
BIT
0
2:1
3
11:4
30:12
FUNCTION
PME Enable
Data Select
Data Scale
PME Status
FUNCTION
Reserved
B2/B3 Support
PCI Bus Power/Clock
Control Enable
Data Register
FUNCTION
Reserved
Downstream Memory 0
Translated Base
FUNCTION
Type Selector
Address Type
Prefetchable Control
Reserved
Base Address Register Size
RWCS
TYPE
TYPE
TYPE
TYPE
RWS
(WS)
(WS)
(WS)
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 102 of 145
DESCRIPTION
0: PME_L assertion is disabled
1: PME_L assertion is enabled
Reset to 0
Data register is not implemented
Reset to 0000
Data register is not implemented
Reset to 00
PME_L is supported
Reset to 0
DESCRIPTION
Reset to 000000
0: B2 / B3 not support for D3hot
Reset to 0
0: PCI Bus Power/Clock Disabled
Reset to 0
Data register is not implemented
Reset to 00h
DESCRIPTION
Reset to 000h
Define the translated base address for downstream memory transactions
whose initiator addresses fall into Downstream Memory 0 (above lower 4K
boundary) address range. The number of bits that are used for translated base
is determined by its setup register (offset 9Ch)
Reset to 00000h
DESCRIPTION
0: Memory space is requested
Reset to 0
00: 32-bit address space
01: 64-bit address space
Reset to 00
0: Non-prefetchable
1: Prefetchable
Reset to 0
Reset to 00h
0: Set the corresponding bit in the Base Address Register to read only.
1: Set the corresponding bit in the Base Address Register to read/write in
order to control the size of the address range.
Reset to 7FFFFh
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110