PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 47

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.4.36 ARBITER PRIORITY REGISTER – OFFSET 48h
Pericom Semiconductor
BIT
11
19:12
20
21
BIT
22
23
24
25
26
27
28
29
FUNCTION
Broken Master Refresh
Enable
Arbiter Fairness Counter
GNT_L Output Toggling
Enable
Reserved
FUNCTION
Arbiter Priority 0
Arbiter Priority 1
Arbiter Priority 2
Arbiter Priority 3
Arbiter Priority 4
Arbiter Priority 5
Arbiter Priority 6
Arbiter Priority 7
TYPE
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
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DESCRIPTION
0: A broken master will be ignored forever after de-asserting its REQ_L for
at least 1 clock
1: Refresh broken master state after all the other masters have been served
once
Reset to 0
08h: These bits are the initialization value of a counter used by the internal
arbiter. It controls the number of PCI bus cycles that the arbiter holds a
device’s PCI bus GNT active after detecting a PCI bus REQ_L from another
device. The counter is reloaded whenever a new PCI bus GNT is asserted.
For every new PCI bus GNT, the counter is armed to decrement when it
detects the new fall of FRAME_L. If the arbiter fairness counter is set to 00h,
the arbiter will not remove a device’s PCI bus GNT until the device has de-
asserted its PCI bus REQ.
Reset to 08h
0: GNT_L not de-asserted after granted master assert FRAME_L
1: GNT_L de-asserts for 1 clock after 2 clocks of the granted master asserting
FRAME_L
Reset to 0
Reset to 0
DESCRIPTION
0: Low priority request to internal PI7C9X110
1: High priority request to internal PI7C9X110
Reset to 1
0: Low priority request to master 1
1: High priority request to master 1
Reset to 0
0: Low priority request to master 2
1: High priority request to master 2
Reset to 0
0: Low priority request to master 3
1: High priority request to master 3
Reset to 0
0: Low priority request to master 4
1: High priority request to master 4
Reset to 0
0: Low priority request to master 5
1: High priority request to master 5
Reset to 0
0: Low priority request to master 6
1: High priority request to master 6
Reset to 0
0: Low priority request to master 7
1: High priority request to master 7
Reset to 0
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110