MSC8156 Freescale Semiconductor, Inc, MSC8156 Datasheet - Page 31

• Manufacturer Part Number: MSC8156
• Description: Six-core Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

2.5.3.2
The DC-level requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The
MSC8156 supports a 2.5 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision 1.0a. The
transmitter specifications are defined in
Freescale Semiconductor
•
SR[1–2]_REF_CLK
SR[1–2]_REF_CLK
— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.
Single-Ended Mode
— The reference clock can also be single-ended. The SR[1–2]_REF_CLK input amplitude (single-ended swing)
— The SR[1–2]_REF_CLK input average voltage must be between 200 and 400 mV.
— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled
Figure 8. Differential Reference Clock Input DC Requirements (External AC-Coupled)
SR[1–2]_REF_CLK
Because the external AC-coupling capacitor blocks the DC-level, the clock driver and the SerDes reference clock
receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection
scheme has its common mode voltage set to GND
swing below and above the command mode voltage GND
requirement for AC-coupled connection scheme.
must be between 400 mV and 800 mV peak-peak (from V
unconnected or tied to ground.
reference clock input requirement for single-ended signaling mode.
externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused
phase (SR[1–2]_REF_CLK) through the same source impedance as the clock input (SR[1–2]_REF_CLK) in use.
SR[1–2]_REF_CLK
DC-Level Requirements for PCI Express Configurations
Figure 9. Single-Ended Reference Clock Input DC Requirements
200 mV < Input Amplitude or Differential Peak < 800 mV
400 mV < SR[1–2]_REF_CLK Input Amplitude < 800 mV
MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 1
Table 11
and the receiver specifications are defined in
SXC
. Each signal wire of the differential inputs is allowed to
SXC
MIN
.
to V
Figure 8
MAX
) with SR[1–2]_REF_CLK either left
shows the SerDes reference clock input
Table
0 V
Vmin > Vcm – 400 mV
Vmax < Vcm + 400 mV
Figure 9
Electrical Characteristics
12.
shows the SerDes
Vcm
31