AD9849 Analog Devices, AD9849 Datasheet - Page 24

• Manufacturer Part Number: AD9849
• Description: CCD Signal Processors with Integrated Timing Driver
• Manufacturer: Analog Devices

AD9848/AD9849
H-Counter Synchronization
The H-Counter reset occurs on the sixth CLI rising edge fol-
lowing the HD falling edge. The PxGA steering is synchronized
with the reset of the internal H-Counter. (See Figure 13.)
(PIXEL COUNTER)
H-COUNTER
PxGA GAIN
REGISTER
CLI
HD
VD
NOTES
1. INTERNAL H-COUNTER IS RESET ON THE SIXTH CLI RISING EDGE FOLLOWING THE HD FALLING EDGE.
2. PxGA STEERING IS SYNCRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).
3. VD FALLING EDGE SHOULD OCCUR ONE CLOCK CYCLE BEFORE HD FALLING EDGE FOR PROPER PxGA LINE SYNCHRONIZATION.
X
X
X
X
X
X
3ns MIN
X
X
3ns MIN
X
X
X
X
X
X
H-COUNTER
RESET
X
X
0
0
1
1
0
2
1
3
4
0
5
1
0
6
1
7
8
0
9
1
10
0
11
1
12
0
14
1
15
0
0
2
1
3
2
2
3
3
4
2
5
3