AD9849 Analog Devices, AD9849 Datasheet - Page 6

• Manufacturer Part Number: AD9849
• Description: CCD Signal Processors with Integrated Timing Driver
• Manufacturer: Analog Devices

TIMING SPECIFICATIONS
AD9848/AD9849
Parameter
MASTER CLOCK (CLI), AD9848
MASTER CLOCK (CLI), AD9849
EXTERNAL MODE CLAMPING
SAMPLE CLOCKS
DATA OUTPUTS
SERIAL INTERFACE
NOTES
1
Specifications subject to change without notice.
Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
CLI Clock Period
CLI High/Low Pulsewidth
Delay From CLI to Internal Pixel Period Position
CLI Clock Period
CLI High/Low Pulsewidth
CLPDM Pulsewidth
CLPOB Pulsewidth
SHP Rising Edge to SHD Rising Edge (AD9848)
SHP Rising Edge to SHD Rising Edge (AD9849)
Output Delay from Programmed Edge
Pipeline Delay
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
1
(C
otherwise noted.)
L
= 20 pF, f
CLI
= 20 MHz [AD9848] or 30 MHz [AD9849], Serial Timing in Figure 3, unless
Symbol
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
CLI
ADC
CLIDLY
CONV
ADC
CDM
COB
S1
S1
OD
SCLK
LS
LH
DS
DH
DV
Min
50
25
33.33
16.67
4
2
20
13
10
10
10
10
10
10
Typ
6
10
20
6
9
Max
Unit
ns
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns