AD9889B Analog Devices, AD9889B Datasheet - Page 8
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AD9889B
Manufacturer Part Number
AD9889B
Description
High Performance HDMI/DVI Transmitter
Manufacturer
Analog Devices
Datasheet
1.AD9889B.pdf
(12 pages)
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AD9889B
BGA
D5, D6, D7, E7
G4, G5, J1
D4, E4, F4, J4, G6,
J6, K6, F7, G7, H9,
J9
F9
F10
E10
E9
G9
G10
1
2
3
I = input, O = output, P = power supply, C = control.
Pin J7 (BGA), Pin 26 (LFCSP), and Pin 33 (LQFP) are dual function pins: I
down control function occurs whenever the state of the pin is changed from its original state at power-up.
For a full description of the 2-wire serial interface and its functionality obtain documentation by contacting NDA from flatpanel_apps@analog.com.
LFCSP
1, 48, 49
15, 16, 17,
64, paddle
on bottom
side
36
35
37
38
34
33
Pin No.
LQFP
63, 64
15, 17, 18, 22,
26, 32, 39, 42,
43, 59, 60, 79,
80
47
49
45
1, 61, 62,
16, 19, 20, 21
46
48
44
Mnemonic
DVDD
PVDD
GND
SDA
SCL
MDA
MCL
DDCSDA
DDCSCL
2
C selection and power-down control. The I
Rev. PrA | Page 8 of 12
Type
P
P
P
C
C
C
C
C
C
3
3
3
3
3
3
1
Description
1.8 V Power Supply for Digital and I/O Power Supply. These
pins supply power to the digital logic and I/Os. They should
be filtered and as quiet as possible.
1.8 V PLL Power Supply. The most sensitive portion of the
AD9889B is the clock generation circuitry. These pins provide
power to the clock PLL. The designer should provide quiet,
noise-free power to these pins.
Ground. The ground return for all circuitry on-chip. It is
recommended that the AD9889B be assembled on a single,
solid ground plane with careful attention given to ground
current paths.
Serial Port Data I/O. This pin serves as the serial port data I/O
slave for register access. Supports CMOS logic levels from
1.8 V to 3.3 V.
Serial Port Data Clock. This pin serves as the serial port data
clock slave for register access. Supports CMOS logic levels
from 1.8 V to 3.3 V.
Serial Port Data I/O Master to HDCP Key EEPROM. Supports
CMOS logic levels from 1.8 V to 3.3 V.
Serial Port Data Clock Master to HDCP Key EEPROM. Supports
CMOS logic levels from 1.8 V to 3.3 V.
Serial Port Data I/O to Receiver. This pin serves as the master
to the DDC bus. 5 V CMOS logic level.
Serial Port Data Clock to Receiver. This pin serves as the
master clock for the DDC bus. 5 V CMOS logic level.
Preliminary Technical Data
2
C selection function occurs at power-up; the power-