MAX11645 Maxim Integrated Products, MAX11645 Datasheet - Page 12

• Manufacturer Part Number: MAX11645
• Description: 2-Wire Serial 12-Bit ADCs
• Manufacturer: Maxim Integrated Products

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
A bus master initiates communication with a slave
device by issuing a START condition followed by a
slave address. When idle, the MAX11644/MAX11645
continuously wait for a START condition followed by
their slave address. When the MAX11644/MAX11645
recognize their slave address, they are ready to accept
or send data. The slave address is factory programmed
to 0110110. The least significant bit (LSB) of the
address byte (R/W) determines whether the master is
writing to or reading from the MAX11644/MAX11645
(R/W = 0 selects a write condition, R/W = 1 selects a
read condition). After receiving the address, the
MAX11644/MAX11645 (slave) issues an acknowledge
by pulling SDA low for one clock cycle.
At power-up, the MAX11644/MAX11645 bus timing is
set for fast-mode (F/S mode), which allows conversion
rates up to 22.2ksps. The MAX11644/MAX11645 must
Figure 7. MAX11644/MAX11645 Slave Address Byte
Figure 8. F/S-Mode to HS-Mode Transfer
12
______________________________________________________________________________________
SDA
SCL
S
SDA
SCL
SEE ORDERING INFORMATION FOR SLAVE ADDRESS OPTIONS AND DETAILS.
0
S
MAX11644/MAX11645
0
0
1
1
0
2
HS-MODE MASTER CODE
Slave Address
1
0
3
Bus Timing
SLAVE ADDRESS
F/S MODE
0
1
4
1
X
5
operate in high-speed mode (HS mode) to achieve con-
version rates up to 94.4ksps. Figure 1 shows the bus
timing for the MAX11644/MAX11645’s 2-wire interface.
At power-up, the MAX11644/MAX11645 bus timing is
set for F/S mode. The bus master selects HS mode by
addressing all devices on the bus with the HS-mode
master code 0000 1XXX (X = don’t care). After suc-
cessfully receiving the HS-mode master code, the
MAX11644/MAX11645 issue a not-acknowledge, allow-
ing SDA to be pulled high for one clock cycle (Figure
8). After the not-acknowledge, the MAX11644/
MAX11645 are in HS mode. The bus master must then
send a repeated START followed by a slave address to
initiate HS mode communication. If the master gener-
ates a STOP condition, the MAX11644/MAX11645
return to F/S mode.
1
X
6
0
X
7
R/W
A
8
A
9
Sr
HS MODE
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HS Mode