AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 65
AT90CAN128-16AE
Manufacturer Part Number
AT90CAN128-16AE
Description
8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
Manufacturer
ATMEL Corporation
Datasheet
1.AT90CAN128-16AE.pdf
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4250C–CAN–03/04
Figure 31. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,
as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is
latched when the system clock goes low. It is clocked into the PINxn Register at the suc-
ceeding positive clock edge. As indicated by the two arrows t
signal transition on the pin will be delayed between ½ and 1½ system clock period
depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as
indicated in Figure 32. The out instruction sets the “SYNC LATCH” signal at the positive
edge of the clock. In this case, the delay t
period.
Figure 32. Synchronization when Reading a Software Assigned Pin Value
INSTRUCTIONS
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
SYSTEM CLK
SYNC LATCH
PINxn
PINxn
r17
r16
r17
out PORTx, r16
XXX
t
pd
pd, max
through the synchronizer is 1 system clock
0x00
0x00
XXX
nop
t
pd
t
0xFF
pd, min
in r17, PINx
in r17, PINx
AT90CAN128
pd,max
and t
pd,min
0xFF
0xFF
, a single
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