AD1821 Analog Devices, AD1821 Datasheet - Page 16

• Manufacturer Part Number: AD1821
• Manufacturer: Analog Devices

AD1821
SERIAL INTERFACES
I
The two I
Figure 9 shows the right-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the rising
edge of the BCLK. The MSB is delayed 16-bit clock periods from an LRCLK transition, so that when there are 64 BCLK periods
per LRCLK period, the LSB of the data will be right-justified to the next LRCLK transition.
Figure 10 shows the I
edge of BCLK. The MSB is left-justified to an LRCLK transition, but with a single BCLK period delay.
Figure 11 shows the left-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the rising
edge of BCLK. The MSB is left-justified to an LRCLK transition, with no MSB delay.
Bidirectional DSP Serial Interface
The AD1821 SoundComm
face port (SPORT). The AD1821 is always the bus master and supplies the frame sync and the serial clock. The AD1821 has four
pins assigned to the SPORT: SDI, SDO, SDFS, and SCLK. The SPORT has two operating modes: monitor and intercept. The
SPORT always monitors the various data streams being processed by the AD1821. In intercept mode, any of the digital data streams
can be manipulated by the DSP before reaching the final ADC or DAC stages.
The SDI and SDO pins handle the serial data input and output of the AD1821. Communication in and out of the AD1821 requires that
bits of data be transmitted after a rising edge of SCLK and sampled on the falling edge of SCLK. The SCLK frequency is always
11 MHz (or 1/3 or XTALI).
DSP Serial Port Interface time slots are mapped as shown in Table I.
2
S Serial Ports
LRCLK
SDATA
LRCLK
LRCLK
SDATA
SDATA
BCLK
BCLK
BCLK
2
S serial ports on the AD1821 accept serial data in the following formats: Right-Justified, I
2
S-justified mode. LRCLK is LO for the left channel and HI for the right channel. Data is valid on the rising
15 14 13 12 11 10 9
15 14 13 12 11 10 9
15 14 13 12 11 10 9
®
Controller transmits and receives both data and control/status information through its DSP serial inter-
LEFT CHANNEL
LEFT CHANNEL
LEFT CHANNEL
Figure 9. Serial Interface Right-Justified Mode
Figure 11. Serial Interface Left-Justified Mode
Figure 10. Serial Interface I
8
8
8
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
–16–
15
2
15
S-Justified Mode
14 13 12 11 10 9
14 13 12 11 10 9
15
14 13 12 11 10 9
RIGHT CHANNEL
RIGHT CHANNEL
RIGHT CHANNEL
8
8
7
7
6
8
6
5
7
5
4
6
2
S-Justified and Left-Justified.
4
3
5
3
4
2
2
3
1
1
0
2
0
1
0
REV. 0