AD1821 Analog Devices, AD1821 Datasheet - Page 6

• Manufacturer Part Number: AD1821
• Manufacturer: Analog Devices

AD1821
TIMING PARAMETERS
Parameter
IOW/IOR Strobe Width
IOW/IOR Rising to IOW/IOR Falling
Write Data Setup to IOW Rising
IOW Falling to Valid Read Data
AEN Setup to IOW/IOR Falling
AEN Hold from IOW/IOR Rising
Adr Setup to IOW/IOR Falling
Adr Hold from IOW/IOR Rising
DACK Rising to IOW/IOR Falling
Data Hold from IOR Rising
Data Hold from IOW Rising
DRQ Hold from IOW/IOR Falling
DACK Hold from IOW/IOR Rising
Data [SDI] Input Setup Time to SCLK*
Data [SDI] Input Hold Time from SCLK*
Frame Sync [SDFS] HI Pulse Width*
Clock [SCLK] to Frame Sync [SDFS]
Clock [SCLK] to Output Data [SDO] Valid*
RESET Pulse Width
BCLK HI Pulse Width
BCLK LO Pulse Width
BCLK Period
LRCLK Setup
SDATA Setup
SDATA Hold
NOTES
*Guaranteed, not tested.
†(All ISA pins MIDI_OUT IOL = 24 mA. Refer to pin description for individual output drive levels.
Specifications subject to change without notice.
DACK (0, 1, 3)
DRQ (0, 1, 3)
Propagation Delay*
PC_A [15:0]
PC_D [7:0]
AEN
IOR
Figure 1. PIO Read Cycle
t
DKSU
t
ADSU
(Guaranteed Over Operating Temperature Range)
t
RDDV
t
AESU
t
STW
t
DKHD
t
DHD1
t
t
ADHD
AEHD
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
STW
BWDN
WDSU
RDDV
AESU
AEHD
ADSU
ADHD
DKSU
DHD1
DHD2
DRHD
DKHD
S
H
FSW
PD
DV
RPWL
DBH
DBL
DBP
DLS
DDS
DDH
–6–
DACK (0, 1, 3)
DRQ (0, 1, 3)
PC_A [15:0]
PC_D [7:0]
IOW
AEN
Min
100
80
10
10
0
10
0
20
15
10
15
10
100
25
25
50
5
5
5
Figure 2. PIO Write Cycle
t
DKSU
t
ADSU
t
AESU
Typ
80
t
STW
Max
40
2
25
15
15
t
WDSU
t
DKHD
t
DHD2
t
ADHD
t
AEHD
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. 0