STK16C88-3 Simtek, STK16C88-3 Datasheet - Page 3

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STK16C88-3

Manufacturer Part Number
STK16C88-3
Description
CMOS Nonvolatile Static RAM
Manufacturer
Simtek
Datasheet

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March 2006
SRAM READ CYCLES #1 & #2
Note f:
Note g: I/O state assumes E, G < V
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
SRAM READ CYCLE #2: E Controlled
DQ (DATA OUT)
DQ (DATA OUT)
NO.
10
11
1
2
3
4
5
6
7
8
9
ADDRESS
ADDRESS
W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
t
t
t
t
t
t
t
t
t
t
t
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
#1, #2
I
CC
G
E
f
g
g
h
h
SYMBOLS
e
d
,
e
t
t
t
t
t
t
t
t
t
t
t
ACS
RC
AA
OE
OH
LZ
HZ
OLZ
OHZ
PA
PS
Alt.
IL
and W > V
STANDBY
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
t
ELICCH
t
t
IH
AXQX
ELQX
10
t
5
6
GLQX
; device is continuously selected.
8
t
GLQV
4
f
t
AVAV
t
2
t
ACTIVE
AVQV
ELQV
1
3
t
AVAV
PARAMETER
2
3
f, g
Document Control # ML0019 rev 0.2
DATA VALID
DATA VALID
t
GHQZ
(V
9
t
EHQZ
STK16C88-3-35
7
CC
MIN
35
t
5
5
0
0
EHICCL
STK16C88-3
11
= 3.0V-3.6V)
MAX
35
35
15
13
13
35
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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