W90210F Winbond Electronics Corp America, W90210F Datasheet - Page 15

• Manufacturer Part Number: W90210F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

endian. AIR[0] is documented in this data sheet. AIR[1] and AIR[2] are reserved for chip testing by Winbond, and their
functions will not be disclosed to users. Attempting to access these two registers may cause programs to be executed
with unpredictable results. Memory configuration registers are used for programming the configuration of W90210F
memory space. AIR[7] is the PCO register, this AIR can only be accessed through the JTAG ICE interface.
Enabling the internal D-cache with MTAIR[0] will invalidate all cache entries without dirty data entries being written back.
Disabling the D-cache, however, will not invalidate cache entries.
automatically written into memory. When a program references the dirty data location, stale data in memory will be
returned. To prevent this, a cache invalidation routine should be performed before the internal D-cache is disabled. The
invalidation routine must flush all cache entries one by one. This will invalidate the cache and also write back any dirty
data.
registers will cause unpredictable result.
Number
12 - 31
Bit
10
11
5.3 Implementation of the PA-RISC instructions
0
1
2
3
4
5
6
7
8
9
5.2.5 W90210F External Interrupt Request register (EIRR; CR23)
5.2.6 AIRs (Architecture Invisible Registers)
There are eight AIRs in the W90210F. AIR[0] controls the internal cache configuration, burst mode, and default
Important:
Disabling the internal D-cache with MTAIR[0] will cause dirty data to be left in the D-Cache and not
AIR[1] and AIR[2] are reserved registers and should never be written to or read from them. Accessing these
CR 26, 27
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
EI[0:4]
Enabling or disabling the internal I-cache with MTAIR[0] will invalidate all I-cache entries automatically.
Others
CR 11
CR 16
00000
10000
01000
11000
00100
10100
01100
11100
00010
10010
01010
11010
-
AIR[0]
AIR[1]
AIR[2]
AIR[3]
AIR[4]
AIR[5]
AIR[6]
AIR[7]
read/write at any privilege level
PSW 'S'=0: read/write by any privilege level
PSW 'S'=1: read/write by privileged software
readable at any privilege level
writable at the most privileged level
Accessible only at most privileged level
Parallel_Int
Timer_Int
Serial_Int
DMA_Int
External
Interrupt
TC_Int
Serial
INTA
INTB
INTC
INTD
-
-
-
Table 5.5 External Interrupt Request Register
Table 5.4 Access of control registers
Table 5.6 W90210F CPU core AIRs
Internal configuration register
PSW register
TMR register
Memory configuration register 1
Memory configuration register 2
Memory configuration register 3
Memory configuration register 4
PCO register (program counter)
Interval Timer (CR16) interrupt request
Serial port interrupt request from COM2
PCI bus INTA# interrupt request
PCI bus INTB# interrupt request
PCI bus INTC# interrupt request
PCI bus INTD# interrupt request
Parallel port interrupt request
Serial port interrupt request from COM1
DMA interrupt request
Timer/Counter interrupt request
Reserved
15
Description
W90210F
Version 1.4, 10/8/97