W90210F Winbond Electronics Corp America, W90210F Datasheet - Page 26

• Manufacturer Part Number: W90210F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

8. Megacells Description
supported. CAS#-before-RAS# refresh cycles are performed periodically, as determined by the refresh timer. The
DRAM controller must arbitrate between access requests and refresh requests. EDO fast page mode and parity check
are also supported.
8.1 DRAM Controller & ROM Controller
8.1.1 DRAM controller
The DRAM controller supports four separate banks of dynamic memory. Either X9 or X36 SIMMs are
For each bank of DRAM, there will be registers to specify the bank base address and the bank DRAM type:
DRAM Type Register is used to program the DRAM type of each bank.
DRAM Timing Register is used to program DRAM timing parameters:
2ah
2bh
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Bank Base Address Register.
Bank Type Register.
[6:7] Write cycle RAS# to CAS# delay.
[4:5] Read cycle RAS# to CAS# delay
[3] Write cycle CAS# pulse width.
[2] CAS# precharge time.
[0:1] RAS# precharge time.
[6:7] Read cycle. CAS# pulse width.
[5] Refresh cycle. CAS# active to RAS# active delay.
[3:4] Refresh cycle. RAS# active to CAS# inactive delay.
[1:2] Refresh cycle. RAS# active pulse width.
[0] Parity check enable.
CPU interface
0 1 2 3 4 5 6 7
Bank
3
Figure 8.2 DRAM Type register programming
Figure 8.1 DRAM controller block diagram
Bank
DRAM Type
2
Bank
DRAM Type Register
CPU core
26
Interface
1
Bus
to
Bank
0
00 : 256K DRAM cell
01 : 1M DRAM cell
10 : 4M DRAM cell
11 : 16M DRAM cell
Bank Base Address
DRAM Type Register
DRAM Configuration
DRAM Timing
Refresh Timer
Registers
Register
Register
RAS#[4]
CAS#[4]
MA[12]
MD[32]
WE#
W90210F
Version 1.4, 10/8/97