W90210F Winbond Electronics Corp America, W90210F Datasheet - Page 32

• Manufacturer Part Number: W90210F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

the counter decrements to zero, the timer will assert the associated interrupt signal. The interrupt signal will assert one
of the 32 external interrupts defined by the EI bits in the control register. When a timer reaches zero, the timer
hardware reloads the counter with the value from the timer initial count register and continues decrementing.
register. These registers are all memory mapped I/O registers.
interrupt signal to interrupt the CPU.
CE bit to zero stops the timer.
remain one until software sets it to zero.
8.3 Timer / Counter
Two 24-bit decrementing timers will be implemented. When the timer's interrupt enable bit is set to one and
Each timer is controlled and initialized by two registers: a timer control register and an timer initial count
Timer Control register:
Timer Initial Count Register:
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Pre-Scalar (PS)
Interrupt Enable bit (IE)
Counter Enable bit (CE)
Timer Interrupt bit (TI)
A 24-bit read/write register for the initial counter value.
TI
: A pre-scalar value can be used to divide the input clock.
0
0
CE
reserved
1 2 3
IE
: The timer sets this bit to one to indicate that it has decrement to zero. This bit
: When IE is set to one and the counter decrements to zero, the timer asserts its
: Setting the CE bit to one causes the timer to begin decrementing. Setting the
7 8
Peripheral
4
Timer/Counter megacell
Interface
Figure 8.7 Timer/Counter Megacell
32
reserved
TICR
TCR
Timer Initial Count
TICR1
TICR2
TCR1
TCR2
23
24
pre-scalar
TCLK
TINT1
TINT2
31
31
W90210F
Version 1.4, 10/8/97