MT93L00A Zarlink Semiconductor, MT93L00A Datasheet - Page 25
MT93L00A
Manufacturer Part Number
MT93L00A
Description
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT93L00A.pdf
(33 pages)
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Preliminary Information
6:5
4:0
7:1
Bit
Bit
IRQ
7
0
res
7
7
Interrupt FIFO Register
Test Register
res
6
0
6
I<4:0>
Name
Name
IRQ
Tirq
res
0
res
5
5
0
res
I4
4
4
Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt
FIFO register is read.
Logic Low indicates that no interrupt is pending and the FIFO is empty.
Unused bits. Always zero
I<4:0> binary code indicates the channel number at which a Tone Detector state
change has occurred.
Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
Reserved bits. Must always be set to zero for normal operation.
Test IRQ: Useful for the application engineer to verify the interrupt service routine.
When high, any change to MTDBI and MTDAI bits of the Main Control Register will
cause an interrupt and its corresponding channel number will be available from the
Interrupt FIFO Register.
When low, normal operation is selected.
res
I3
3
3
res
I2
2
2
res
I1
1
1
Tirq
I0
0
0
Read Address:
Reset Value:
Read/Write Address: 411
Reset Value:
Description
Description
410
00
00
H
H
H
.
H
.
(Read only)
MT93L00A
25
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