IXS839S1T-R Clare, Inc., IXS839S1T-R Datasheet - Page 13

• Manufacturer Part Number: IXS839S1T-R
• Description: Synchronous Buck Mosfet Driver
• Manufacturer: Clare, Inc.

waiting for the voltage on the High Side Gate
Driver Output pin to reach 1 volt, the overlap
protection circuit ensures that Q1 is OFF before Q2
turns on.
Similarly, when the PWM input transitions high, Q2
begins to turn OFF, and Q1 turns ON after the
overlap protection circuit detects that the voltage at
the Low-Side Gate Driver output has dropped
below 1 volt. Once the driver output voltage falls
below 1 volt, the overlap protection circuit initiates
a delay timer that adds additional delay set by the
external capacitor connected to the DLY pin. This
programmable delay circuit allows adjustments to
optimize performance based on the switching
characteristics of the external power MOSFET.
Low-Side Driver Shutdown
The IXS839A/B include a Low-Side Gate Driver
shutdown feature. A logic low signal at the LSD
input shuts down the Low Side Gate Driver, and in
turn the synchronous rectifier FET. This signal can
be used to achieve maximum battery life under
light load conditions and maximum efficiency under
heavy
conditions, LSD should be high so that the
synchronous switch is controlled by the PWM
signal for maximum efficiency. Under light load
conditions the LSD can be low to disable the Low
Side Gate Driver so the switching current can be
minimized.
Shutdown
For optimal system power management, the
IXS839A/B drivers can be shut down to conserve
power. When the SD pin is high, the IXS839A/B
are enabled for normal operation. Pulling the SD
pin low forces the HGD and LGD outputs low, and
reduces the supply current by disabling the internal
reference.
Under Voltage Lockout (IXS839 and IXS839B)
The Under Voltage Lockout (UVLO) circuit holds
both driver outputs low during VDD supply ramp-
up. The UVLO logic becomes active and in control
of the driver outputs at a supply voltage of no
greater than 1.5 V. When the supply voltage rises
above the UVLO upper threshold the circuit allows
the PWM input to control the drivers.
load
IXYS
conditions.
Under
heavy
load
13
Application Information
Supply Capacitor Selection
A 1 uF ceramic bypass capacitor is recommended
for the VDD input to provide noise suppression.
The bypass capacitor should be located as close
as possible to the IXS939/A/B.
Bootstrap Circuit
The bootstrap circuit requires a charge storage
capacitor CBST and a Schottky diode DBST, as
shown in Figure 1. Selecting these components
should be done with consideration of the electrical
characteristics of the high-side FET chosen.
The bootstrap capacitor voltage rating must
exceed the maximum input voltage, (VIN) + the
maximum VDD voltage. The capacitance is
determined using the following equation:
Where, QGATE is the total gate charge of Q1, and
∆VBST is the allowable Q1 voltage droop.
To maximize the available drive for Q1 in the
bootstrap circuit a Schottky diode is recommended.
The bootstrap diode voltage rating must exceed
the maximum input voltage, (VIN) + the maximum
VDD voltage. The average forward current can be
estimated by:
where F
frequency. Peak surge current is dependent on the
source impedance of the 5V supply and the ESR
of CBST, and should be checked in-circuit.
Delay Capacitor Selection
A ceramic capacitor is recommended for the DLY
input, and should be located as close a possible to
the DLY pin.
Printed Circuit Board Layout Considerations
Use
designing printed circuit boards:
1. Trace out the high current paths and use short,
2. Locate the VDD bypass capacitor as close as
3. Connect the source of the Lower MOSFET,
wide traces to make these connections.
possible to the VDD and PGND pins.
(Q2) as close as possible the PGND.
the
MAX
IXS839 / IXS839A / IXS839B
following
I
F(AVG)
is the maximum PWM input switching
C
BST
= Q
=
Q
∆V
GATE
GATE
general
BST
X F
MAX
guidelines
when