MC74LVX50DG ON Semiconductor, MC74LVX50DG Datasheet

MC74LVX50DG

Manufacturer Part Number

MC74LVX50DG

Description

IC BUFFER HEX NON-INVERT 14SOIC

Manufacturer

ON Semiconductor

Series

74LVXr

Datasheets

1.MC74LVX50DTR2G.pdf (10 pages)

2.MC74LVX50DG.pdf (11 pages)

Specifications of MC74LVX50DG

Logic Type

Buffer/Line Driver, Non-Inverting

Number Of Elements

Number Of Bits Per Element

Current - Output High, Low

4mA, 4mA

Voltage - Supply

2 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

14-SOIC (3.9mm Width), 14-SOL

Logic Family

LVX

Number Of Channels Per Chip

Polarity

Non-Inverting

Supply Voltage (max)

3.6 V

Supply Voltage (min)

2 V

Maximum Operating Temperature

+ 85 C

Mounting Style

SMD/SMT

High Level Output Current

- 4 mA

Low Level Output Current

4 mA

Maximum Power Dissipation

500 mW

Minimum Operating Temperature

- 40 C

Number Of Lines (input / Output)

6 / 6

Propagation Delay Time

13.6 ns at 2.7 V, 9.7 ns at 3.3 V

Logic Device Type

Buffer, Non Inverting

Supply Voltage Range

2V To 3.6V

Logic Case Style

SOIC

No. Of Pins

Operating Temperature Range

-40Â°C To +85Â°C

Filter Terminals

SMD

Rohs Compliant

Yes

Family Type

LVX

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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MC74LVX50

Hex Buffer

fabricated with silicon gate CMOS technology.

output which provides high noise immunity and stable output. The

inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V

systems to 3.0 V systems.

Features

•

May, 2011 − Rev. 4

The MC74LVX50 is an advanced high speed CMOS buffer

The internal circuit is composed of three stages, including a buffered

High Speed: t

Low Power Dissipation: I

High Noise Immunity: V

Power Down Protection Provided on Inputs

Balanced Propagation Delays

Designed for 2.0 V to 3.6 V Operating Range

Low Noise: V

These Devices are Pb−Free and are RoHS Compliant

OLP

= 4.1 ns (Typ) at V

= 0.5 V (Max)

NIH

= 2 mA (Max) at T

= V

NIL

= 28% V

= 3.3 V

= 25°C

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

(Note: Microdot may be in either location)

LVX50 = Specific Device Code

WL, L

WW, W = Work Week

G or G

ORDERING INFORMATION

http://onsemi.com

CASE 751A

CASE 948G

D SUFFIX

DT SUFFIX

TSSOP−14

SOEIAJ−14

SOIC−14

= Assembly Location

= Wafer Lot

= Year

= Pb−Free Package

CASE 965

M SUFFIX

Publication Order Number:

DIAGRAMS

MARKING

MC74LVX50/D

AWLYWW

LVX50G

ALYWG

LVX50

ALYWG

LVX

Related parts for MC74LVX50DG

MC74LVX50DG Summary of contents

Page 1

MC74LVX50 Hex Buffer The MC74LVX50 is an advanced high speed CMOS buffer fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffered output which provides high noise immunity and stable output. The inputs ...

Page 2

... Figure 1. Logic Diagram 14−Lead Pinout (Top View) ORDERING INFORMATION Device MC74LVX50DG MC74LVX50DR2G MC74LVX50DTG MC74LVX50DTR2G MC74LVX50MG MC74LVX50MELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free ...

Page 3

MAXIMUM RATINGS Symbol V DC Supply Voltage Input Voltage Output Voltage OUT I DC Input Diode Current Output Diode Current Output Sink Current OUT I DC Supply Current ...

Page 4

DC ELECTRICAL CHARACTERISTICS Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Symbol Parameter Î Î Î Î Î Î Î Î Î ...

Page 5

A t PLH 50 Figure 3. Switching Waveforms EMBOSSED CARRIER DIMENSIONS (See Notes 9 and 10) Tape Size Max 8 mm 4.35 mm 1.0 mm 1.5 mm 1.75 mm (0.179”) Min ...

Page 6

K t COVER SEE NOTE 11 FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC AROUND MIN. TAPE AND COMPONENTS SHALL PASS AROUND RADIUS “R” WITHOUT DAMAGE BENDING RADIUS MAXIMUM COMPONENT ROTATION 10° TYPICAL ...

Page 7

MIN (0.06”) 20.2 mm MIN A (0.795”) FULL RADIUS Figure 7. Reel Dimensions REEL DIMENSIONS Tape Size T&R Suffix A Max 8 mm T1, T2 178 mm (7” T3, T4 330 mm (13” ...

Page 8

TAPE TRAILER (Connected to Reel Hub) CAVITY TOP TAPE NO COMPONENTS TAPE 160 mm MIN Figure 10. TSSOP and SOIC R2 Reel Configuration/Orientation TAPE UTILIZATION BY PACKAGE Tape Size COMPONENTS DIRECTION OF ...

Page 9

G −T− SEATING 14 PL PLANE 0.25 (0.010 PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE 0.25 (0.010 ...

Page 10

K 14X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT. 1 0.15 (0.006 −V− C 0.10 (0.004) −T− G SEATING D PLANE 14X 0.36 PACKAGE DIMENSIONS TSSOP−14 DT SUFFIX ...

Page 11

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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