IDT71V2556S Integrated Device Technology, IDT71V2556S Datasheet - Page 10

• Manufacturer Part Number: IDT71V2556S
• Description: 128k X 36, 256k X 18 3.3v Synchronous Zbt Srams 2.5v I/o, Burst Counter Pipelined Outputs
• Manufacturer: Integrated Device Technology

Interleaved Burst Sequence Table
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Linear Burst Sequence Table
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram
NOTES:
1. This assumes CEN, CE
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
First Address
Second Address
Fourth Address
First Address
Second Address
Fourth Address
Third Address
Third Address
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
(R/W, ADV/LD, BWx)
delay from the rising edge of clock.
I/O [0:31], I/O P[1:4]
CONTROL
ADDRESS
(A0 - A16)
CLOCK
DATA
CYCLE
(1)
(1)
(2)
(2)
(2)
1
, CE
2
, CE
D/Q27
n+29
C29
A29
2
are all true.
D/Q28
n+30
C30
A30
A1
A1
0
0
0
0
1
1
1
1
Sequence 1
Sequence 1
(1)
D/Q29
n+31
C31
A31
(LBO=V
A0
A0
0
0
0
0
1
1
1
1
(LBO=V
D/Q30
n+32
6.42
SS
C32
A32
10
)
A1
A1
0
0
0
0
1
1
1
1
Sequence 2
Sequence 2
DD
D/Q31
n+33
C33
A33
)
A0
A0
0
0
0
0
1
1
1
1
Commercial and Industrial Temperature Ranges
D/Q32
n+34
C34
A34
A1
A1
0
0
0
0
1
1
1
1
Sequence 3
Sequence 3
D/Q33
n+35
C35
A35
A0
A0
0
0
0
0
1
1
1
1
D/Q34
n+36
C36
A36
A1
A1
0
0
0
0
1
1
1
1
Sequence 4
Sequence 4
4875 drw 03
D/Q35
n+37
C37
A37
4875 tbl 10
A0
A0
4875 tbl 11
0
0
0
0
1
1
1
1
,