HT48CA0-1 Holtek Semiconductor, HT48CA0-1 Datasheet - Page 10

• Manufacturer Part Number: HT48CA0-1
• Description: (HT48RA0-1 / HT48CA0-1) Remote Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

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Input/Output Ports
There are an 8-bit bidirectional input/output port, a 6-bit
input with 2-bit I/O port and one-bit output port in the
HT48RA0-1/HT48CA0-1, labeled PA, PB and PC which
are mapped to [12H], [14H], [16H] of the RAM, respec-
tively. Each bit of PA can be selected as NMOS output or
Schmitt trigger with pull-high resistor by software in-
struction. PB0~PB1 have the same structure with PA,
while PB2~PB7 can only be used for input operation
(Schmitt trigger with pull-high resistors). PC is only
one-bit output port shares the pin with carrier output. If
the level option is selected, the PC is CMOS output.
Both PA and PB for the input operation, these ports are
non-latched, that is, the inputs should be ready at the T2
rising edge of the instruction MOV A, [m] (m=12H or
14H). For PA, PB0~PB1 and PC output operation, all
data are latched and remain unchanged until the output
latch is rewritten.
When the PA and PB0~PB1 is used for input operation,
it should be noted that before reading data from pads, a
NMOS device. That is, the instruction SET [m].i (i=0~7
for PA, i=0~1 for PB) is executed first to disable related
NMOS device, and then MOV A, [m] to get stable data.
Rev. 1.40
1 should be written to the related bits to disable the
PA, PB Input/Output Lines
PB Input Lines
10
After chip reset, PA and PB remain at a high level input
line while PC remain at high level output, if the level op-
tion is selected.
Each bit of PA, PB0~PB1 and PC output latches can be
set or cleared by the SET [m].i and CLR [m].i
(m=12H, 14H or 16H) instructions respectively.
Some instructions first input data and then follow the
output operations. For example, SET [m].i , CLR [m] ,
the CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or to the
accumulator.
Each line of PB has a wake-up capability to the device
by code option. The highest seven bits of PC are not
physically implemented, on reading them a 0 is re-
turned and writing results in a no-operation.
CPL [m] , CPLA [m] read the entire port states into
HT48RA0-1/HT48CA0-1
December 21, 2005