ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 109

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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Mode 1, PWM and Counter
PWM can be used to generate precise pulses of known
width and duty cycle on the TA pin. The timer is clocked by
the instruction clock. An underflow causes the timer register
to be reloaded alternately from the TCRA and TCRB regis-
ters, and optionally causes the TA output to toggle. Thus,
the values stored in the TCRA and TCRB registers control
the high and low time of the signal produced on TA. In the
PWM mode timer/counter 2 can either be used as a simple
system timer or as an external event counter. The counter
can be loaded by the user software with a specific value and
T can generate an interrupt after the pre-programmed num-
ber of external events have been received on the TB input.
Figure 14-4 shows a block diagram of the timer operating in
mode1. In the PWM mode of operation counter I, TCNT1,
functions as the time base for the PWM timer. Counter 1
counts down at the clock rate selected via the counter 1
clock selector. When an underflow occurs, the timer register
is reloaded alternately from the TCRA and TCRB registers,
and counting proceeds downward from the loaded value. At
the first underflow, the timer is loaded from TCRA, the sec-
ond time from TCRB, the third time from TCRA, and so on.
Note that every time the counter is stopped the selection of
“No-Clock” via the counter 1 clock selector it obtains its first
reload value after it has been re-started from the TCRA reg-
ister. On reset, and every time this mode is entered, the first
reload in this mode is from register TCRA.
Timer 1
Timer 2
Selector
Clock
Clock
Clock
Multi-Function 16-Bit Timer (MFT16)
Figure 14-4. Mode 1, PWM and Counter
Reload A = Time 1
Timer/Counter 1
Reload B = Time 2
Timer/Counter 2
TCNT1
TCRA
TCNT2
TCRB
Underflow
Underflow
109
The timer can be configured to toggle the TA output bit on
underflow. This results in the generation of a clock signal on
TA with the width and duty cycle controlled by the values
stored in the TCRA and TCRB registers. This PWM clock is
processor-independent because, once the timer is set up,
no more interaction is required by the user software, and
hence the CPU, to generate a continuous PWM signal. Soft-
ware can select the initial value of the PWM output signal as
either high or low. See “Timer I/O Functions” on page 113
for additional details. The timer can be configured to gener-
ate separate interrupts on reload from TCRA and TCRB.
The interrupts can be enabled or disabled under software
control. The TAPND or TBPND flags, respectively, which
are set by the hardware on occurrence of a timer reload, in-
dicate which interrupt occurred. (See Section 14.4.2 on
page 113 for detailed information.)
In this mode of operation, the second timer/counter2 can be
used as either a simple system timer, an external event
counter, or as a pulse accumulate counter. Counter TCNT2
counts down with the clock selected via the counter2 clock
selector, and can be configured to generate an interrupt on
underflow, if enabled by the TDIEN bit. (See Section 14.4.2
on page 113 for detailed information.)
TAPND
TDPND
TBPND
TAIEN
TBIEN
TDIEN
TAEN
Interrupt 1
Interrupt 2
Interrupt 1
Timer
Timer
Timer
TA
TB