ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 120

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

16.2.1 Reset
The ADC status and control registers are reset to their de-
fault values in the following two ways:
Cold Reset. Upon power-up, an internal power-up detect
circuit generates a reset cycle. See Section 2.3 on page 26.
Warm Reset. When the chip is powered up and a positive
pulse is applied on the Host Master Reset (HMR) input pin,
a reset cycle is performed. See also HMR pin functionality
in Table 2-1 on page 21.
16.2.2 Reference Voltage
The analog input voltages are converted relative to a refer-
ence voltage. See both Figure 16-1 and "Bit 1 - Internal
VREF (INTREF)" on page 123 for details. For DC specifica-
tions, see Table 19-5 on page 134. The ADC can use either
an internal or external reference voltage, as follows:
Internal Reference Voltage. This is generated on-chip by
a high accuracy circuit, which can be internally connected
to the converter. The on-chip reference is used when the IN-
TREF bit of the ADCCNT1 register is set (1). The accuracy
of the internal reference is higher than required by most ap-
plications.
External Reference Voltage. To apply an external refer-
ence voltage to the V
must be disabled. In this case, the external reference volt-
age should be within the actual AGND and AV
curacy of the conversion is directly dependent on the
precision of the external reference. To use this option, the
INTREF bit of the ADCCNT1 register must be cleared (0).
Note 1: The V
internal and external configurations, a 0.47 F filtering ca-
pacitor, C
as shown in Figure 16-1.
Note 2: It is recommended to use an internal reference volt-
age instead of an external one. Internal reference voltage is
far more accurate, and also enables/disables control for re-
ducing the current consumption to zero. If an input voltage
of more than 2.5 V must be converted, use an external re-
sistor divider as detailed in Figure 16-2. Using the external
reference voltage configuration with V
AV
cy, higher current consumption and causes difficulties in
measuring AV
the value of AV
16.2.3 Input Signal Range
The ADC performs a linear conversion of the input voltage
signal to an unsigned digital representation. The input sig-
nal should be applied relative to the AGND pin, and should
range from a minimum of AGND to a maximum of the actual
V
An input signal of zero (ground) is converted to 00h. An in-
put signal equal to (255/256)
When the input signal is higher than the maximum input
range, the ADC generates a result which may be lower than
FFh. To prevent this, a simple resistor divider should be
used before the analog input (see Figure 16-2). The divider
should be calculated so that its output is lower than V
for the maximum input signal, as specified in Table 19-5 on
page 134.
REF
CC
.
is not recommended, since it results in lower accura-
1
, should be placed as close as possible to V
CC
REF
CC
voltage. Also, the code is dependent on
used, 3.3 V or 5.0 V.
pin filters the internal reference. In both
REF
pin, the internal reference voltage
*
V
REF
Analog to Digital Converter (ADC) - January 1998
is converted as FFh.
REF
connected to
CC
. The ac-
REFmin
REF
,
120
16.2.4 ADC Clock
The ADC clock is generated by the on-chip clock multiplier
(see Chapter 7 on page 76). This clock can be divided by 1,
2, 4, 8, 16, 32 or 64, by programming the pre-scaler located
at CDIV of the ADCCNT3 Register. The ADC clock must op-
erate at a rate lower than 1 MHz. The Clock Divider (see
Figure 16-1) allows ADC usage in systems with a higher
clock rate. CDIV must be programmed prior to enabling the
ADC (i.e., while ADCEN of the ADCCNT1 Register is 0).
16.2.5 Initializing and Enabling the ADC
The PC87570 wakes up after power-up with the ADC dis-
abled (ADCEN of the ADCCNT1 Register is cleared). In this
state, all ADC activities are halted, and its current consump-
tion is reduced to zero.
Initializing the ADC. The ADC must be initialized prior to
being enabled. The following fields/bits must be set:
Enabling the ADC. The ADC is enabled by setting ADCEN
of the ADCCNT1 Register to 1. The internal reference volt-
age is enabled by setting INTREF of this same register to 1.
The internal reference cannot be enabled if the ADC is not
enabled.
After the ADC is enabled, its internal circuits need a maxi-
mum activation delay of 100 s. The internal reference volt-
age needs a typical 50 s delay to charge the external
filtering capacitor of 0.47 F, present on V
Figure 16-1.
Both ADCEN and INTREF can be set in one write operation
to the ADCCNT1 Register so that their delays begin simul-
taneously. Before attempting to start the first conversion cy-
cle, the software should wait 100 s after enabling the ADC
and the internal reference. See the T
Table 19-5 on page 134. When re-enabling the ADC after it
has been disabled, the software should again wait 100 s.
V
V
C
IN0
IN0
CDIV
DELAY
INTE
INTREF ADCCNT1 Internal reference voltage
2
Field/Bit Register
Signal
Input
R
is an optional capacitor for noise filtering
V
Figure 16-2. Analog Input Resistor Divider
=
1
IN
Table 16-1. ADC Initialization Settings
R
V
1
REFmin
R
+R
2
ADCCNT3 ADC clock rate
ADCCNT3 Required sampling time
ADCCNT1 Interrupt mode (if required)
2
R
2
V
INmax
C
2
*
source enable (if required)
V
IN0
Description
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ACT
REF
PC87570
, as shown in
parameter in
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