ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 122

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

16.3 OPERATION MODES
The ADC supports four modes of automated operation, as
defined by SCAN and CONT of the ADCCNT2 Register. Ta-
ble 16-3 summarizes ADC operation in the various modes.
Channel and mode selection (CHANNEL, SCAN and CONT
Mode
One
Channel,
Single
Conversion
One
Channel,
Continuous
Conversion
Four
Channel
Scan,
Single
Conversion
Four
Channel
Scan,
Continuous
Conversion
Register Bits
SCAN CONT
ADCCNT2
0
0
1
1
0
1
0
1
One conversion is performed for the channel specified by CHANNEL of the ADCCNT2
Register. When the conversion is completed:
Continuous conversions are performed for the channel specified by CHANNEL of the
ADCCNT2 Register. The next conversion starts only after a pause defined by DELAY of the
ADCCNT3 Register. The hardware does not clear START of the ADCCNT2 Register.
When a conversion is completed:
Repetitive conversions are started until START of the ADCCNT2 Register is cleared by the
software. When this occurs:
A conversion is performed for four channels, starting with the channel defined in CHANNEL of
the ADCCNT2 Register. After completion of each conversion, the selector of the input
multiplexer is incremented. Conversion for the next channel is started after the sampling time
delay, defined by DELAY of the ADCCNT3 Register. The conversion stops after all four
channels are converted.
The following procedure is implemented:
Conversion of the selected four channels is continuously repeated. Each conversion cycle is
performed as in “Four Channel Scan, Single Conversion” mode, but the hardware does not
clear START of the ADCCNT2 Register.
When a conversion cycle is completed and if START is still set, a new four channel conversion
cycle is started. When the conversion of all four channels is completed:
Repetitive conversion cycles are started until the START bit is cleared by software. When this
occurs:
The result is placed in the ADDATA0 Register.
START of the ADCCNT2 Register is cleared.
EOC of the ADCST Register is set.
The interrupt request signal is asserted (1) if INTE of the ADCCNT1 Register is set.
The consecutive results are placed in the four data registers cyclically, starting from
ADDATA0.
The last conversion result is pointed to by BUFPTR of the ADCST Register.
When all the four data registers are loaded, EOC of the ADCST Register is set.
If interrupts are enabled (INTE of the ADCCNT1 Register is set), an interrupt is issued to
the ICU.
Any currently executing conversion is completed.
EOC of the ADCST Register is set.
No new conversion is started.
The last conversion result is pointed to by BUFPTR of the ADCST Register.
The results are placed in the ADDATA0-3 Registers for channels 1-4, respectively.
When all four channels have been converted, START of the ADCCNT2 Register is cleared
by hardware, and EOC of the ADCST Register is set.
If INTE of the ADCCNT1 Register is set, an interrupt is issued.
START is not cleared.
EOC is set.
The interrupt signal is asserted if INTE=1.
The currently executing conversion cycle of a 4-channel burst is completed.
EOC of the ADCST Register is set.
No new conversion is started.
The last conversion result is pointed to by BUFPTR of the ADCST Register.
Analog to Digital Converter (ADC) - January 1998
Table 16-3. ADC Operation Modes
122
of the ADCCNT2 Register) should be changed only when
no conversion is in progress (i.e., START of the ADCCNT2
Register and BUSY of the ADCST Register are both 0).
In the scan modes, CHANNEL points to the first channel to
be converted. The other three channels use a modulo-8
counting scheme (channel 7 is followed by channel 0).
Description
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