ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 72

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

Power On
This is the normal state when the PC87570 is powered on.
This state may be initiated by various events in addition to
physically switching the system on. The PC system and the
PC87570 device are powered by V
Note: The APC does not function when the 32.768 KHz
6.5.4
In the Power On state, the APC is powered by V
falls to the level of V
state and switches to V
When power returns after power-off, the APC enables the
generation of an APC-ON interrupt after a delay of 1 sec-
ond.
If V
functions and APC cease functioning.
If neither V
Power state. It is initialized when it leaves this state.
6.5.5
The APC checks when activation conditions are met, and
generates the APC-ON/APC-OFF interrupt signals accord-
ingly. The APC-ON/APC-OFF interrupt signals are active-
high pulses.
APC-ON interrupt is generated, when:
APC-OFF interrupt is generated, when:
6.5.6
Power Up
When power is first applied to the RTC, the APC registers
are initialized to the default values defined in APCR1,
APCR2 and APSR. See Table 6-5. This situation is defined
by the appearance of V
The APC powers-up when the RTC supply is applied from
any source. It is in Power On state only when V
plied.
Power Off
The APC is in Power Off state when it is powered by V
Upon entering Power Off state, the following occurs:
•
•
•
Time Match Enable bit (bit 0 of APCR2) is 1 and there is
a match between the RTC and the time specified in the
pre-determined date registers.
User software must ensure unused date/time fields are
coherent to ensure a reliable comparison of valid bits.
RING Enable bit (bit 3 of APCR2) is 1 and one of the fol-
lowing occurs:
— Bit 2 of APCR2 is 0 and a high-to-low transition is de-
— Bit 2 0f APCR2 is 1 and a train of pulses is detected
A 1 is written to Software Off Command bit (bit 5 of
APCR1).
The RING pin (for detecting telephone line incoming sig-
nals for fax, modem or voice communication) is masked
(high).
BAT
oscillator is not running.
tected on the RING input pin.
on the RING input pin.
System Power Switching Logic
falls below V
APC-ON/APC-OFF Interrupt Signals
Entering Power States
CC
or V
BAT
CCON
LOWBAT
is available, the system goes to No
BAT
BAT
, the APC enters the Power Off
.
or V
, the oscillator, timekeeping
Real-Time Clock (RTC) and Advanced Power Control (APC)
CC
CC.
with no previous power.
CC
CC
. If V
is ap-
BAT
CC
.
72
6.5.7
The second, minute and hour values of the pre-determined
wake-up times are contained in the Seconds Alarm, Minutes
Alarm and Hours Alarm registers respectively (register off-
sets 01, 03 and 05 in all banks). The Day of Week, Date of
Month Month, Year and Century of the pre-determined date
is held in Bank 2, registers, offsets 43h-46h and 48h. These
eight registers are compared with the Seconds, Minutes,
Hours, Day of Week, Date of Month, Month, Year and Cen-
tury registers correspondingly (register offsets 00, 02, 04, 06,
07, 08, 09 in all banks and register offset 48 in Bank 1).
6.5.8
An incoming telephone call is an event that may generate
an APC-ON interrupt in order to deal with a pending incom-
ing voice, fax or modem communication.
The PC87570 can detect a RING pulse falling edge, or a
RING pulse train with a frequency of at least 16 Hz that lasts
at least 0.19 seconds.
When APCR2.RPTDM is set, the APC is in a RING pulse
train detection mode and the existence of falling edges on
RING is monitored in time slots of 62.5 ms (16 Hz cycle
time). A RING pulse train detect event occurs if falling
edge(s) of RING are detected in three consecutive time
slots, following a time slot in which no falling edge of RING
is detected.
This method of detecting a RING pulse train filters out (does
not detect) a RING pulse train of less then 11 Hz, might de-
tect a RING pulse train of 11 Hz to 16 Hz, and guarantees
detection of a RING pulse train of at least 16 Hz.
If APCR2.RPTDM is cleared, a single falling edge on the
RING input will generate a RING wakeup event.
6.6 APC REGISTERS
The APC registers reside in the APC Bank 2 memory. The
RAM Lock register also resides in this bank. See Table 6-9
on page 75.
The APC control registers are not affected by system reset.
They are initialized to 0 only when power is applied for the
first time; i.e., application of either V
previous voltage is present.
Offset Mnemonic
The signal remain masked until 1 second after exit from
Power Off state (i.e., 1 second after switching from V
to V
When the 1 second delay expires, new events can gen-
erate the APC-ON interrupt. In addition, if a time match
occurs during Power Off, the APC “remembers” to send
an APC-ON interrupt.
In case Power Off was entered before a host Software
Off Command was executed, an APC-ON interrupt is
generated for RING and/or predetermined wake-up
match events detected prior to entering Power Off
state.
40h
41h
42h
47h
CC
Predetermined Wake-Up
Ring Signal Event
).
.
Table 6-6. APC Control Registers
APCR1
APCR2
APSR
RLR
APC Control Register 1
APC Control Register 2
APC Status Register
RAM Lock Register
Register Name
BAT
or V
CC
www.national.com
, when no
BAT