UPD78F4046GC-3B9 NEC, UPD78F4046GC-3B9 Datasheet - Page 25

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UPD78F4046GC-3B9

Manufacturer Part Number
UPD78F4046GC-3B9
Description
16-BIT SINGLE-CHIP MICROCONTROLLER
Manufacturer
NEC
Datasheet
Serial Operation (T
Other Operations (T
AC Timing Test Points
Serial clock cycle time
Serial clock low-level width
Serial clock high-level width
SI1, SI2 setup time
(to SCK1, SCK2 )
SI1, SI2 hold time
(from SCK1, SCK2 )
Delay time from SCK1, SCK2
to SO1, SO2 output
NMI high-/low-level width
INTP0 to INTP6 high-/low-level width t
TI2, TI3 high-/low-level width
RESET high-/low-level width
Remarks 1. T
Remarks 1. t
V
0 V
DD
Parameter
Parameter
2. t
2. t
3. NIn: Bit n of NPC (n = 0 to 6)
When NIn = 0, t
When NIn = 1, t
CYK
CYSMP
CYK
SFT
A
= 1/f
= 1/f
A
is a value set by software. The minimum value is t
= –10 to +70˚C, V
= –10 to +70˚C, V
is a sampling clock set by software in the noise protection control register (NPC).
CLK
CLK
0.8V
0.8 V
(f
(f
DD
CLK
CLK
t
t
t
CYSMP
CYSMP
or 2.2 V
WNIH
WITH
WTIH
WRSH
t
t
t
t
t
t
CYSK
WSKL
WSKH
SSSK
HSSK
DSBSK
is internal system clock frequency)
is internal system clock frequency)
Symbol
Symbol
, t
, t
, t
, t
WITL
WTIL
WNIL
= t
= t
WRSL
DD
DD
CYK
CYK
= 4.5 to 5.5 V, V
= 4.5 to 5.5 V, V
Data Sheet U11447EJ2V0DS00
SCK1, SCK2 output BRG
SCK1, SCK2 input
SCK1, SCK2 output BRG
SCK1, SCK2 input
SCK1, SCK2 output BRG
SCK1, SCK2 input
R = 1 k , C = 100 pF
4
Test points
Conditions
Conditions
SS
SS
= 0 V)
= 0 V)
External clock
External clock
External clock
CYK
8.
0.8V
0.5T
0.5T
DD
MIN.
MIN.
T
500
210
210
80
80
10
10
SFT
SFT
SFT
0
4
4
or 2.2 V
–40
–40
0.8 V
PD78F4046
MAX.
MAX.
150
t
t
CYSMP
CYSMP
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
25

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